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求教DM8168 PCIe GEN2

studying
Intellectual 810 points


大家好：

       我在做DM8168和C6678通过PCIe通信的项目，C6678作为EP，DM8168作为RC，两者都使用的EVM板。

       现在的问题是：C6678的PCIe寄存器以及DM8168的PCIe寄存器都配置的是x2 mode（通过PL_GEN2寄存器的值0x20F可以看出），但最后发现仅仅使用一个lane（通过LINK_STAT_CTRL寄存器的值可以看出，DM8168该值为0x30120008，C6678该值为0x10120080）；我想请问下这是什么原因造成的？为什么我对DM8168以及C6678均enable了x2 lane，最后却显示仅仅使用了一条lane？它们链路训练是成功的，还有个PL_LINK_CTRL寄存器的值DM8168和C6678都是0x30120。

       谢谢！

  • 0
    TI__Guru**** 155073 points

    Studying，

    请问两个芯片的LINK_CAP.MAX_LINK_WIDTH是否配置为2？

  • 0 回复 Chris Meng
    Intellectual 810 points

    您好：

       DM8168的LINK_CAP值为0x135422；C6678的LINK_CAP值为0x35422，说明MAX_LINK_WIDTH配置为2了。

  • 0 回复 studying
    TI__Guru**** 155073 points

    Studying,

    请问两颗芯片的PCIe在硬件上是如何连接的？是做在一块板子上用PCB走线连接的？

    能否使能DM816x驱动里面的debug信息，看看枚举的时候是否有有用的信息？

    http://processors.wiki.ti.com/index.php/TI81XX_PCIe_FAQs#How_can_I_enable_debugging_the_PCI.2FPCIe_enumeration_and_configuration.3F

  • 0 回复 Chris Meng
    Intellectual 810 points

    您好：

         两颗芯片的PCIe是通过EVM板预留的PCIe卡槽相连的，没有做在一块板子上。

        我觉得这种情况是否和PCIe的参考时钟有关？C6678的参考时钟是由DM8168提供的，如果配置成x2，PCIe参考时钟应该设置为多少？100MHZ？

        这是启动的时候关于PCIe的打印信息：

        

    ti81xx_pcie: Invoking PCI BIOS...
    ti81xx_pcie: Setting up Host Controller...
    ti81xx_pcie: Register base mapped @0xd0820000
    ti81xx_pcie: Starting PCI scan...
    PCI: bus0: Fast back to back transfers disabled
    PCI: bus1: Fast back to back transfers disabled
    ti81xx_pcie: PCI scan done.
    pci 0000:00:00.0: BAR 9: assigned [mem 0x20000000-0x217fffff pref]
    pci 0000:00:00.0: BAR 8: assigned [mem 0x21800000-0x218fffff]
    pci 0000:01:00.0: BAR 3: assigned [mem 0x20000000-0x20ffffff pref]
    pci 0000:01:00.0: BAR 3: set to [mem 0x20000000-0x20ffffff pref] (PCI address [0x20000000-0x20ffffff])
    pci 0000:01:00.0: BAR 2: assigned [mem 0x21000000-0x213fffff pref]
    pci 0000:01:00.0: BAR 2: set to [mem 0x21000000-0x213fffff pref] (PCI address [0x21000000-0x213fffff])
    pci 0000:01:00.0: BAR 0: assigned [mem 0x21800000-0x218fffff]
    pci 0000:01:00.0: BAR 0: set to [mem 0x21800000-0x218fffff] (PCI address [0x21800000-0x218fffff])
    pci 0000:01:00.0: BAR 1: assigned [mem 0x21400000-0x2147ffff pref]
    pci 0000:01:00.0: BAR 1: set to [mem 0x21400000-0x2147ffff pref] (PCI address [0x21400000-0x2147ffff])
    pci 0000:01:00.0: BAR 5: assigned [mem 0x21480000-0x2148ffff pref]
    pci 0000:01:00.0: BAR 5: set to [mem 0x21480000-0x2148ffff pref] (PCI address [0x21480000-0x2148ffff])
    pci 0000:01:00.0: BAR 4: assigned [mem 0x21490000-0x21490fff pref]
    pci 0000:01:00.0: BAR 4: set to [mem 0x21490000-0x21490fff pref] (PCI address [0x21490000-0x21490fff])
    pci 0000:00:00.0: PCI bridge to [bus 01-01]
    pci 0000:00:00.0: bridge window [io disabled]
    pci 0000:00:00.0: bridge window [mem 0x21800000-0x218fffff]
    pci 0000:00:00.0: bridge window [mem 0x20000000-0x217fffff pref]
    PCI: enabling device 0000:00:00.0 (0140 -> 0143)

    以下是链路训练后通过指令lspci -vvv的打印信息：

    00:00.0 Class 0604: Device 104c:b800 (rev 01)
    Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Region 0: Memory at <ignored> (32-bit, non-prefetchable)
    Region 1: Memory at <ignored> (32-bit, prefetchable)
    Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
    I/O behind bridge: 0000f000-00000fff
    Memory behind bridge: 21800000-218fffff
    Prefetchable memory behind bridge: 20000000-217fffff
    Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
    BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
    PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
    Capabilities: [40] Power Management version 3
    Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
    Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
    Address: 0000000000000000 Data: 0000
    Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00
    DevCap: MaxPayload 256 bytes, PhantFunc 0
    ExtTag- RBE+
    DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
    RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
    MaxPayload 128 bytes, MaxReadReq 512 bytes
    DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
    LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s, Exit Latency L0s <2us, L1 <64us
    ClockPM- Surprise- LLActRep+ BwNot-
    LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk-
    ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
    LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
    RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
    RootCap: CRSVisible-
    RootSta: PME ReqID 0000, PMEStatus- PMEPending-
    DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-
    DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
    LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
    Compliance De-emphasis: -6dB
    LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
    Capabilities: [100 v1] Advanced Error Reporting
    UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
    UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
    UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
    CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
    CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
    AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-

    01:00.0 Class 0480: Device 104c:b005 (rev 01)
    Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Interrupt: pin A routed to IRQ 48
    Region 0: Memory at 21800000 (32-bit, non-prefetchable) [size=1M]
    Region 1: Memory at 21400000 (32-bit, prefetchable) [size=512K]
    Region 2: Memory at 21000000 (32-bit, prefetchable) [size=4M]
    Region 3: Memory at 20000000 (32-bit, prefetchable) [size=16M]
    Region 4: Memory at 21490000 (32-bit, prefetchable) [size=4K]
    Region 5: Memory at 21480000 (32-bit, prefetchable) [size=64K]
    Capabilities: [40] Power Management version 3
    Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
    Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
    Address: 0000000000000000 Data: 0000
    Capabilities: [70] Express (v2) Endpoint, MSI 00
    DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <1us, L1 <8us
    ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
    DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
    RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
    MaxPayload 128 bytes, MaxReadReq 512 bytes
    DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
    LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s, Exit Latency L0s <2us, L1 <64us
    ClockPM- Surprise- LLActRep- BwNot-
    LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
    ExtSynch+ ClockPM- AutWidDis- BWInt- AutBWInt-
    LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
    DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported
    DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
    LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
    Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
    Compliance De-emphasis: -6dB
    LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
    EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
    Capabilities: [100 v1] Advanced Error Reporting
    UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
    UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
    UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
    CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
    CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
    AERCap: First Error Pointer: 00, GenCap+ CGenEn+ ChkCap+ ChkEn

    非常感谢您的帮助！