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ddr2如何测试啊？怎么memory browser全是0000FFFE,还没发更改…………哎，真是急死了，哇哇的……………………
请问用的哪款器件？
DDR2配置了么？
您好，请问怎么配置啊？ddr2是三星的K4T51163QQ-BCE7，求给指导，万谢啊………………
我用*(volatile unsigned int *)(0xC0000005 )可以读出0000FFFE的值就是65534，但是值写不进去
// 0xB000 0008 SDCR 0x00134632 // 0xB000 000C SDRCR 0xC0000260 // 0xB000 0010 SDTIMR1 0x264A2A09 // 0xB000 0014 SDTIMR2 0x4412C722 // 0xB000 001C SDCR2 0x00000000 // 0xB000 00E4 DRPYC1R 0x000000C3 DEVICE_DDRConfig() { unsigned int j; unsigned int tmp_SDCR; // Enable the Clock to EMIFDDR SDRAM PSC1_LPSC_enable(PD0, LPSC_DDR); // Begin VTP Calibration VTPIO_CTL &= ~0x00000040; // Clear POWERDN VTPIO_CTL &= ~0x00000080; // Clear LOCK VTPIO_CTL |= 0x00002000; // Set CLKRZ in case it was cleared before (VTP looks for CLKRZ edge transition) VTPIO_CTL &= ~0x00002000; // Clear CLKRZ (Use read-modify-write to ensure 1 VTP cycle wait for previous instruction) VTPIO_CTL |= 0x00002000; // Set CLKRZ (Use read-modify-write to ensure 1 VTP cycle wait for previous instruction) j = 0; // Polling READY bit to see when VTP calibration is done while((VTPIO_CTL & 0x00008000) == 0) { if( j++ > VTP_TIMEOUT ) { GEL_TextOut("\tVTP Ready timeout\n","Output",1,1,1); break; } } VTPIO_CTL |= 0x00000080; // Set LOCK bit for static calibration mode VTPIO_CTL |= 0x00000040; // Set POWERDN bit to power down VTP module // End VTP Calibration VTPIO_CTL |= 0x00004000; // Set IOPWRDN to allow powerdown of input receivers when PWRDNEN is set // ********************************************************************************************** // Setting based 1Gb DDR2 Samsung K4T1G164QF-BCF8 // Config DDR timings DRPYC1R = (0x0 << 8) | // Reserved (0x1 << 7) | // EXT_STRBEN (0x1 << 6) | // PWRDNEN (0x0 << 3) | // Reserved (0x3 << 0); // RL // DRPYC1R Value = 0x000000C3 if( DDR_DEBUG ) { // Configure EMIF with max timings for more slack // Try this if memory is not stable DRPYC1R |= 0x7; // RL } EMIFDDR_SDCR |= 0x00800000; // Set BOOTUNLOCK // Settings depending on DDR2 tmp_SDCR = (0x0 << 25) | // MSDRAMEN (0x1 << 20); // DDR2EN GEL_TextOut("\tUsing DDR2 settings\n","Output",1,1,1); EMIFDDR_SDCR = tmp_SDCR | // Settings that change depending on DDR2 or MDDR (EMIFDDR_SDCR & 0xF0000000) | // Reserved (0x0 << 27) | // DDR2TERM1 (0x0 << 26) | // IBANK_POS (0x0 << 24) | // DDRDRIVE1 (0x0 << 23) | // BOOTUNLOCK (0x0 << 22) | // DDR2DDQS (0x0 << 21) | // DDR2TERM0 (0x0 << 19) | // DDRDLL_DIS (0x0 << 18) | // DDRDRIVE0 (0x1 << 17) | // DDREN (0x1 << 16) | // SDRAMEN (0x1 << 15) | // TIMUNLOCK (0x1 << 14) | // NM (0x0 << 12) | // Reserved (0x3 << 9) | // CL (0x0 << 7) | // Reserved (0x3 << 4) | // IBANK (0x0 << 3) | // Reserved (0x2 << 0); // PAGESIZE EMIFDDR_SDCR2 = 0x00000000; // IBANK_POS set to 0 so this register does not apply if( DDR_DEBUG ) { // Configure EMIF with max timings for more slack // Try this if memory is not stable EMIFDDR_SDTIMR1 = (0x7F << 25) | // tRFC (0x07 << 22) | // tRP (0x07 << 19) | // tRCD (0x07 << 16) | // tWR (0x1F << 11) | // tRAS (0x1F << 6) | // tRC (0x07 << 3) | // tRRD (EMIFDDR_SDTIMR1 & 0x4) | // Reserved (0x03 << 0); // tWTR EMIFDDR_SDTIMR2 = (EMIFDDR_SDTIMR2 & 0x80000000) | // Reserved (((unsigned int) ((70000 / 3400) - 0.5)) << 27) | // tRASMAX (original 7812.5) (0x3 << 25) | // tXP (0x0 << 23) | // tODT (Not supported) (0x7F << 16) | // tXSNR (0xFF << 8) | // tXSRD (0x07 << 5) | // tRTP (1 Cycle) (0x1F << 0); // tCKE GEL_TextOut("\tDDR Timings Configured for Debug\n","Output",1,1,1); } else { // Let float -> integer truncate handle minus 1; Safer to round up for timings EMIFDDR_SDTIMR1 = (19 << 25) | // tRFC (1 << 22) | // tRP (1 << 19) | // tRCD (2 << 16) | // tWR (5 << 11) | // tRAS (8 << 6) | // tRC (1 << 3) | // tRRD (0 << 2) | // Reserved (1 << 0); // tWTR EMIFDDR_SDTIMR2 = (EMIFDDR_SDTIMR2 & 0x80000000) | // Reserved (8 << 27) | // tRASMAX (2 << 25) | // tXP (0 << 23) | // tODT (Not supported) (18 << 16) | // tXSNR (tXSR for mDDR) (199 << 8) | // tXSRD (tXSR for mDDR) (1 << 5) | // tRTP (2 << 0); // tCKE } EMIFDDR_SDCR &= ~0x00008000; // Clear TIMUNLOCK // Let float -> integer truncate handle RR round-down; Safer to round down for refresh rate EMIFDDR_SDRCR = (0x1 << 31) | // LPMODEN (Required for LPSC SyncReset/Enable) (0x1 << 30) | // MCLKSTOPEN (Required for LPSC SyncReset/Enable) (0x0 << 24) | // Reserved (0x0 << 23) | // SR_PD (0x0 << 16) | // Reserved (0x260 << 0); // RR // SyncReset the Clock to EMIFDDR SDRAM PSC1_LPSC_SyncReset(PD0, LPSC_DDR); // Enable the Clock to EMIFDDR SDRAM PSC1_LPSC_enable(PD0, LPSC_DDR); // Disable self-refresh EMIFDDR_SDRCR &= ~0xC0000000; EMIFDDR_PBBPR = 0x10; }
这是创龙的gel文件，我配置了加色的，请问我就运行行不？
主处理器是TMS320C6748
#1. 阅读C6748 TRM手册spruh79A章节13.3.2 Configuring Memory-Mapped Registers to Meet DDR2 Specification，了解要配哪些东西。
#2. 根据自己板子上用的DDR的手册参数修改gel文件里的对应的参数。
#3. 也可利用DDR参数配置工具：http://processors.wiki.ti.com/index.php/Programming_mDDR/DDR2_EMIF_on_OMAP-L1x/C674x
