你好，目前小弟正学习PCIE的调试，有一下几点想请TI的技术大牛帮忙解释一下。
1.1 PCIE initialization process
PCIE初始化
The PCIE initialization process in the STK is implemented to match real PCIE network initialization as much as possible.
Following is the basic flow for RC and EP remote loopback test:
EP initializes BAR mask and properties, which indicates the PCI address space request to RC. In the STK, one BAR is initialized for prefetchable space, one BAR is initialized for non-prefetchable space.
EP 端步骤一：EP写BAR mask（1010h，1014等）表示PCIe地址及空间大小的寄存器，提供给RC。//实际操作中，我这个配置由LINUX端来完成，也能完成连接和数据收发
EP initializes MSI Capabilities Register, which indicates the number of interrupt vectors request to RC.
EP 端步骤二：EP写中断向量号到MSI_CAP（1050h）寄存器，提供给RC。//实际上EP写了0x000B7005到1050h
EP starts physical link training, and waits for link training completion…
EP 端步骤三：EP启动物理链接训练，等待链接完成//实验结果，连接完成
RC initializes the base and limit of PCIE address space.
RC 端步骤四：初始化基地址和PCIE地址空间//实验结果，连接完成
RC starts physical link training, and waits for link training completion …
RC 端步骤五：RC开始物理链接训练，此时EP正在等待链接//实验结果，连接完成
RC reads BAR mask and properties from EP, allocates PCI address space accordingly, writes the PCI start address to the BAR register of EP, and then RC configures its own outbound memory regions to map the PCI address space to its own local access window.
RC 端步骤六：RC端读取BAR mask（远程+1010h，1014等），并分配地址空间。写PCI起始地址到EP端的BAR寄存器（300h-33ch），然后RC配置linux自身的outboud地址映射到本地存储空间//实验结果，连接完成
EP polls the BAR register value, once it gets valid PCIE address set by RC, EP configures its own inbound memory regions to map the PCI address space to its own local address space.
RC 端步骤七：EP端查询BAR寄存器（300h-33ch）的值，一旦有被RC配置，EP就设置自身的inbound地址映射到本地的存储空间//实验结果，连接完成
RC reads the MSI capabilities register of EP, allocates interrupt vectors accordingly, writes start index and number of the allocated interrupt vectors to EP MSI registers.
RC 端步骤八：RC读取MSI_CAP（远程1050h）寄存器的值，同时分配中断向量号，写start index（这个是什么？）和中断向量号到MSI_IRQ寄存器（远程054h）。//实验结果，未完成，不明白这一步RC如何操作。
1.1.1.1 EP to RC MSI interrupt test
EP发送MSI中断到RC
EP MSI interrupts are generated by a PCIe 32-bit memory write transaction from EP PCIE window to MSI_IRQ register in RC. To generate MSI interrupts, following steps need to be taken:
1. Ensure that the MSI support has been enabled in the device (Set MSI_EN bit in MSI Capabilities Register (MSI_CAP).)
确认MSI_CAP（1050h）中的MSI_EN已经被使能//实测MSI_CAP = 0x00b70005
2. EP Reads the value of the MSI Data Register in the local PCIe configuration space and determines the number of MSI vectors allocated from RC, generates the MSI_DATA which will be used to write to MSI_IRQ
EP读取MSI_DATA（105ch），这样EP就得到了RC的中断向量号，到时候产生中断就是将这个值写到MSI_IRQ（054h）//失败，读上来的MSI_DATA值都是0
3. EP issues a memory write transaction to the RC MSI_IRQ register’s mapping address in EP’s outbound window. In RC, the access to MSI_IRQ goes through BAR0 with default mapping.
EP发布一个内存写传输中断到EP端的outbound，地址映射到RC 端的MSI_IRQ寄存器。//失败
In PCIE STK test, if RC runs on core 0, to generate MSI interrupt to core 0, the MSI_data is set as “8” (DNUM+8).
在PCIE STK测试中，EP要发送一个MSI中断到RC，MSI_data（原105ch，不是64bit模式，1050h）需要被设置成8(DNUM+8)//这个MSI_data的设置由EP端来写还是RC写，什么时候写？DNUM是什么值？//失败
本人实际调试中，RC: Linux; EP:TMS320C6655；平台：sys/bios。能正常完成数据收发，但无法完成MSI中断。
感谢解答
