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6678的CORESEL[3:0]、 LRESET 、NMI管脚为输入管脚，接到FPGA中，FPGA怎么知道何时控制这些管脚跳变呀？在fpga程序中，我一直让这些信号为高电平,可以么？
请参考Kyestone hardware design guide获取这些管脚的时序。重点参考POWER ON sequence章节
http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprabi2&fileType=pdf
时序我看到了，时序图我明白。不明白的地方是，FPGA怎么知道需要使能某个核的复位或者不可屏蔽中断？
