最近在做NOR flahs驱动，参考ICE板子代码，现在问题是，一往NORflash 地址空间进行读写时，就错误退出。不知是何原因。大神们帮忙看下，谢谢。
示波器测量信号时,并没有片选信号。
ARM:am3354
NORflash:s29GL01
配置代码：
//enable clock to GPMC module
//----- 1、时钟使能
HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL ) |=
CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE;
//check to see if enabled
while( (HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL) & CM_PER_GPMC_CLKCTRL_IDLEST) !=
(CM_PER_GPMC_CLKCTRL_IDLEST_FUNC << CM_PER_GPMC_CLKCTRL_IDLEST_SHIFT));
//reset the GPMC module
//----- 2、复位GPMC模块
HWREG(GPMC_BASE + GPMC_SYSCONFIG ) |= GPMC_SYSCONFIG_SOFTRESET;
while((HWREG(GPMC_BASE + GPMC_SYSSTATUS) & GPMC_SYSSTATUS_RESETDONE) ==
GPMC_SYSSTATUS_RESETDONE_RSTONGOING);
//Configure to no idle
//----- 3、配置为no idle模式
temp = HWREG(GPMC_BASE + GPMC_SYSCONFIG);
temp &= ~GPMC_SYSCONFIG_IDLEMODE;
temp |= GPMC_SYSCONFIG_IDLEMODE_NOIDLE << GPMC_SYSCONFIG_IDLEMODE_SHIFT;
HWREG(GPMC_BASE + GPMC_SYSCONFIG) = temp;
HWREG(GPMC_BASE + GPMC_IRQENABLE) = 0x0;
HWREG(GPMC_BASE + GPMC_TIMEOUT_CONTROL) = 0x0;
//configure for NOR and granularity x2
//----- 4、配置参数,包括
//----- 位宽
//----- wait pin选择
//----- mux mode 选择
HWREG(GPMC_BASE + GPMC_CONFIG1(csNum)) = (0x0 |
(GPMC_CONFIG1_0_DEVICESIZE_SIXTEENBITS <<
GPMC_CONFIG1_0_DEVICESIZE_SHIFT ) |
(GPMC_CONFIG1_0_WAITPINSELECT_W1<<
GPMC_CONFIG1_0_WAITPINSELECT_SHIFT)|
(GPMC_CONFIG1_0_ATTACHEDDEVICEPAGELENGTH_SIXTEEN <<
GPMC_CONFIG1_0_ATTACHEDDEVICEPAGELENGTH_SHIFT )
);
//----- ontime
//----- de-assert-rd
//----- de-assert-wr
HWREG(GPMC_BASE + GPMC_CONFIG2(csNum)) = (0x0 |
(CS_ON_TIME ) |
(CS_DEASSERT_RD << GPMC_CONFIG2_0_CSRDOFFTIME_SHIFT) |
(CS_DEASSERT_WR << GPMC_CONFIG2_0_CSWROFFTIME_SHIFT));
//----- adv-assert
//----- adv-assert-rd
//----- adv-assert-wr
HWREG(GPMC_BASE + GPMC_CONFIG3(csNum)) = (0x0 |
(ADV_ASSERT << GPMC_CONFIG3_0_ADVONTIME_SHIFT) |
(ADV_DEASSERT_RD << GPMC_CONFIG3_0_ADVRDOFFTIME_SHIFT) |
(ADV_DEASSERT_WR << GPMC_CONFIG3_0_ADVWROFFTIME_SHIFT));
//----- OE-ASSERT
//----- OE-DE-ASSERT
//----- WE-ASSERT
//----- WE-DE-ASSERT
HWREG(GPMC_BASE + GPMC_CONFIG4(csNum)) = (0x0 |
(OE_ASSERT << GPMC_CONFIG4_0_OEONTIME_SHIFT) |
(OE_DEASSERT << GPMC_CONFIG4_0_OEOFFTIME_SHIFT) |
(WE_ASSERT << GPMC_CONFIG4_0_WEONTIME_SHIFT)|
(WE_DEASSERT << GPMC_CONFIG4_0_WEOFFTIME_SHIFT));
//----- RD-CYCLE
//----- WR-CYCLE
//----- RD-ACCESS
HWREG(GPMC_BASE + GPMC_CONFIG5(csNum)) = (0x0 |
(CFG_5_RD_CYCLE_TIM << GPMC_CONFIG5_0_RDCYCLETIME_SHIFT)|
(CFG_5_WR_CYCLE_TIM << GPMC_CONFIG5_0_WRCYCLETIME_SHIFT)|
(CFG_5_RD_ACCESS_TIM << GPMC_CONFIG5_0_RDACCESSTIME_SHIFT)
);
//----- CYCLE2CYCLESAMECSEN
//----- CYC2CYC_DELAY
//----- WR_DATA_ON_ADMUX
//----- WR_ACCESS_TIM
HWREG(GPMC_BASE + GPMC_CONFIG6(csNum)) = (0x0 |
(GPMC_CONFIG6_0_CYCLE2CYCLESAMECSEN_C2CDELAY <<
GPMC_CONFIG6_0_CYCLE2CYCLESAMECSEN_SHIFT) |
(CYC2CYC_DELAY << GPMC_CONFIG6_0_CYCLE2CYCLEDELAY_SHIFT) |
(WR_DATA_ON_ADMUX << GPMC_CONFIG6_0_WRDATAONADMUXBUS_SHIFT)|
(CFG_6_WR_ACCESS_TIM << GPMC_CONFIG6_0_WRACCESSTIME_SHIFT));
//----- BASE ADDR
//----- CS VALID
//-----
HWREG(GPMC_BASE + GPMC_CONFIG7(0)) =
(CFG_7_BASE_ADDR << GPMC_CONFIG7_0_BASEADDRESS_SHIFT) |
(0x1 << GPMC_CONFIG7_0_CSVALID_SHIFT) |
(CFG_7_MASK << GPMC_CONFIG7_0_MASKADDRESS_SHIFT);
其中
#define GPMC_BASE 0x50000000
#define FLASH_BASE ( 0x10000000)
