Part Number: AM2754-Q1
Chip / core: AM275x, issue observed and instrumented on the C7x DSP core (C75SS0_0), FreeRTOS.
SDK: freertos_sdk_am275x_12_01_00_28
Hi,
We are seeing the channel interleave phase of an AASRC GROUP output drift over time, and would like to know whether this is expected behaviour or a configuration mistake on our side.
AASRC is configured as a single GROUP channel with 12 channels. The input clock zone is slaved to an external A2B frame sync (McASP2_AFSR); the output clock zone is derived from a local 24.576 MHz reference clock. The two domains are therefore asynchronous, and we measured them to be 7.2 ppm apart — absorbing that offset is exactly why we use AASRC here.
To isolate the problem we inject a mono test tone on A2B media channel 0 and keep the other 11 channels digitally silent, then log which interleave lane carries the signal on each side of AASRC. At the AASRC input buffer the tone stays on lane 0 for the entire run. At the AASRC output buffer it migrates: 0 -> 11 -> 10 -> 9 -> ... -> 1 -> 0, wrapping through all 12 lanes.
The direction is always the same (towards lower lane index, consistent with the output domain being the faster one), but the step size is not constant — most events move the phase by 1 lane, while some events move it by more than one lane at once. Over a 27.7 minute run the phase wrapped through all 12 lanes, at irregular intervals ranging from 50 s to 355 s.
What makes this hard to handle is that nothing in the driver reports it. During that same run the AASRC error callback fired 0 times, the application dropped 0 input blocks, the 4-deep transaction ring never starved (3-4 transactions in flight throughout), and we verified by instrumentation that our transaction-to-buffer mapping never diverged (0 mismatches). The audio itself is clean — no glitches, no dropouts — only the channel positions shift.
Our questions:
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In GROUP mode with asynchronous input/output clock zones, is the 12-channel interleave phase of the output DMA stream guaranteed to remain stable indefinitely? If not, is this a known limitation of GROUP mode?
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A 12-channel GROUP maps onto 6 stereo SRC pairs sharing one DMA stream. Are the rate-compensation decisions of those 6 pairs shared, or does each pair decide independently? If independent, a divergence of N samples between pairs would rotate the interleave by N positions, which would match both the single-lane and the multi-lane steps we observe. Is that the mechanism?
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Is there a register or API to read the current output FIFO level per stereo pair, or the interleave phase of the GROUP? We need a way to detect and re-align the phase that does not depend on audio content — our current probe only works because we can inject a single-channel test tone.
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For this use case (resampling 12 A2B media channels from an external clock-slave domain into the local domain), is a single GROUP(12) the recommended configuration, or should we use 6 independent STEREO channels with separate DMA streams so that the pairs cannot drift relative to each other?
Full configuration, reproduction steps, detection method and raw logs are in the sections below.
Thanks,
Hu
