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4 Boot Processes The boot process is determined by the boot configuration selected, as described in section 5. Up to three types of boot processes are available: No boot process: The CPU begins direct execution from the memory located at address 0. If SDRAM is used in the system, the CPU is held until SDRAM initialization is complete. Operation is undefined if invalid code is located at address 0. ROM boot process: The program located in external ROM is copied to address 0 by the DMA controller. Although the boot process begins when the device is released from external reset, this transfer occurs while the CPU is internally stalled. For the C620x/C670x DSP, these values are expected to be stored in little-endian format in the external memory, typically a ROM device. The transfer is automatically done by the DMA controller as a single-frame block transfer from the ROM to address 0. The DMA copies 64K bytes from CE1 to address 0, using default ROM timings. After completion of the block transfer, the CPU is unstalled and allowed to run from address 0. Host boot process: The CPU is internally stalled while the remainder of the device is released. During this period, an external host can initialize the CPU memory space as necessary through the host interface, including internal configuration registers, such as those that control the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must set the DSPINT to complete the boot process. This transition causes the boot configuration logic to unstall the CPU. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is stalled. Also, DSPINT unstalls the CPU only if the host boot process is selected. All memory may be written to and read by the host. This allows for the host to verify what it sends to the processor, if required. After the CPU is unstalled, the CPU needs to clear the DSPINT bit; otherwise, no more DSPINTs can be received.
