在研究BOOTMODE时察觉PLL发现出问题
在Quick Setup Guide中看到的Switch设定如下
SW5[8:1] = 00001000
其中BM_GPIO[13:11]=SW5[6:4] = 001
设定为66.67MHz
但文件都指出DSP Core Clock为100MHz
请问是设定错误?还是没参考DIP的设定
谢谢
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在研究BOOTMODE时察觉PLL发现出问题
在Quick Setup Guide中看到的Switch设定如下
SW5[8:1] = 00001000
其中BM_GPIO[13:11]=SW5[6:4] = 001
设定为66.67MHz
但文件都指出DSP Core Clock为100MHz
请问是设定错误?还是没参考DIP的设定
谢谢
EVM上的DIP开关经过了CPLD的处理转换,你最好读一下寄存器DEVSTAT看看DSP最后被设置的模式是什么。
HI Allen Yin:
我目前查到的设定是
| 0 | LENDIAN | 1 = System is operating in Little Endian mode |
| 3-1 | Boot Device | 5 = I2C |
| 9-4 | Parameter Index | value = 0 |
| 10 | Speed | 0 = I2C slow mode |
| 12-11 | Address | 1 = Boot from I2C EEPROM at I2C bus address 0x51 |
| 13 | Mode | 0 = Master mode |
| 15-14 | PCIESSMODE[1:0] | 00b = PCIe in End-point mode |
| 16 | PCIESSEN | 0 = PCIe module disabled |
原来当选择I2C 时, PLL项目就成为I2C的设定
而PLL部分文中指出
2.5.2.6.1 "In this mode, the device will make the initial read of the I2C EEPROM while the PLL is in bypass mode."
谢谢