DM8127上cache配置疑惑

DM8127上cache默认配置如下（FC_RMAN_IRES_c6xdsp.cfg）：

/* Disable caching for HWspinlock addresses */
Cache.MAR0_31    = 0x00000000;  /* 0x00000000 - 0x1FFFFFFF --> NOT CACHEABLE */
Cache.MAR32_63   = 0x00000000;  /* 0x20000000 - 0x3FFFFFFF --> NOT CACHEABLE */

/* Config/EDMA registers cache disabled */
Cache.MAR64_95   = 0x00000000;  /* 0x40000000 - 0x5FFFFFFF --> NOT CACHEABLE */
Cache.MAR96_127  = 0x00000000;  /* 0x60000000 - 0x7FFFFFFF --> NOT CACHEABLE */

/* cache settings for 1st 512MB DDR */
Cache.MAR128_159 = 0x0000FF00;  /* 0x80000000 - 0x87FFFFFF --> NOT CACHEABLE */
                                /* 0x88000000 - 0x8FFFFFFF -->     CACHEABLE */
                                /* 0x90000000 - 0x9FFFFFFF --> NOT CACHEABLE */

/* cache settings for 2nd 512MB DDR */
Cache.MAR160_191 = 0x0FFF0000;  /* 0xA0000000 - 0xAFFFFFFF --> NOT CACHEABLE */
                                /* 0xB0000000 - 0xBBFFFFFF -->     CACHEABLE */
                                /* 0xBC000000 - 0xBFFFFFFF --> NOT CACHEABLE */

/* cache settings for 3rd 512MB DDR */
Cache.MAR192_223 = 0x00000000;  /* 0xC0000000 - 0xDFFFFFFF --> NOT CACHEABLE */

/* cache settings for 4th 512MB DDR */
Cache.MAR224_255 = 0x00000000;  /* 0xE0000000 - 0xFFFFFFFF --> NOT CACHEABLE */

而在config_512M.bld中

var KB=1024;
var MB=KB*KB;
var GB=KB*KB*KB;

var DDR3_ADDR                = 0x80000000;
var DDR3_SIZE                = 1 * GB;
var DDR3_ADDR_256_REG0_START = 0x80000000;
var DDR3_ADDR_256_REG0_END   = 0x90000000;
var DDR3_ADDR_256_REG1_START = 0xB0000000;
var DDR3_ADDR_256_REG1_END   = 0xC0000000;



var OCMC0_ADDR                 = 0x40300000;
var OCMC1_ADDR                 = 0x40400000;
var OCMC_SIZE                      = 256*KB;

/* first 256MB */
var LINUX_SIZE                 = 80*MB;
var CMEM_SIZE                  = 64*MB 
var SR1_SIZE                   = 60*MB;
var VIDEO_M3_CODE_SIZE         = 3*MB;
var VIDEO_M3_DATA_SIZE         = 14*MB;
var DSS_M3_CODE_SIZE           = 2*MB;
var DSS_M3_DATA_SIZE           = 22*MB;
var DSP_CODE_SIZE              = 1*MB;
var DSP_DATA_SIZE              = 10*MB;

/* second 256MB */
var TILER_SIZE                 = 128*MB; /* Reducing this to fix Vid Frame Alloc failures. Need to fix */ /* MUST be aligned on 128MB boundary */
var SR2_FRAME_BUFFER_SIZE      = 105*MB;  
var SR0_SIZE                                         = 16*MB;
var HDVPSS_DESC_SIZE           = 2*MB;
var HDVPSS_SHARED_SIZE         = 2*MB;
var NOTIFY_SHARED_SIZE         = 2*MB;
var REMOTE_DEBUG_SIZE          = 1*MB;

根据cache配置

Cache.MAR128_159 = 0x0000FF00;
Cache.MAR160_191 = 0x0FFF0000;
512M内存中CMEM中有16MB是cacheable，SR1、VIDEO_M3_CODE、VIDEO_M3_DATA、DSS_M3_CODE、DSS_M3_DATA、DSP_CODE、DSP_DATA、TILER全部
cacheable，SR2_FRAME_BUFFER中有64MB是cacheable。
我的疑惑：
1. cacheable是不是只用配置DSP_CODE、DSP_DATA即可？毕竟FC_RMAN_IRES_c6xdsp.cfg是在配置DSP上的CACHE。
2. 默认配置为什么要设置 部分CMEM、SR1、VIDEO_M3_CODE、VIDEO_M3_DATA、DSS_M3_CODE、DSS_M3_DATA、TILER和部分SR2_FRAME_BUFFER cacheable?