AM4379中PRU运行编码器Hiperface DSL协议是有关其状态寄存器相关问题

你的这个测试，现在描述的问题是指，在b这个step上面，你尝试往这个寄存器里面写东西，但是写入后，在c处做读出的校验却发现貌似没有写成功。是这个意思吧？ 然后因为没有写成功，导致后面的if判断过不去，是吗？

是的，首先在b上往寄存器里写1011，如果下一个语句去读的话，读出来的数据是正确的，之后在c处再去读取，发现数据又恢复成了1001，导致后面的if判断过不去。

你看下原版英文版本中对这个寄存器的描述：

这个不是绝对的控制，他是会受到本身PRU的一些状态和外设交互影响的，你在对他进行的设置的时候，可以通过打印bit15 run state去check当前的状态，看你在这个bit改变的前后，PRU的状态如何。

Processor Enable: This bit controls whether or not the PRU is
allowed to fetch new instructions.
If this bit is de-asserted while the PRU is currently running and has
completed the initial cycle of a multi-cycle instruction (LBxO, SBxO,
etc.), the current instruction will be allowed to complete before the
PRU pauses execution.
Otherwise, the PRU will halt immediately.
Because of the unpredictability/timing sensitivity of the instruction
execution loop, this bit is not a reliable indication of whether or not
the PRU is currently running.
The pru_state bit should be consulted for an absolute indication of
the run state of the core.
When the PRU is halted, its internal state remains coherent therefore
this bit can be reasserted without issuing a software reset and the
PRU will resume processing exactly where it left off in the instruction
stream.
0h (R/W) = PRU is disabled.
1h (R/W) = PRU is enabled.

请问有没有关于PRU与外设之间交互影响的详细资料介绍？