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MMU Overview A memory management unit (MMU) is a hardware component responsible for handling accesses to memory requested by a processing unit, DMA controller, or other bus requestor. MMU functions include: • Translation of initiator internal (virtual) addresses to physical addresses (that is, virtual memory management) • Preventing an initiator from making accesses to unmapped pages of the system memory This device includes the following MMUs: • Two top-level (system) MMUs: – MMU1 dedicated to EDMA Transfer Controller 0 (TC0), and EDMA Transfer Controller 1 (TC1) – MMU2 dedicated to PCIe_SS1, and PCIeSS2 • One MMU inside the MPU (dual Cortex ® -A15) subsystem – MPU_MMU. This MMU is integrated in the Cortex-A15 processor. • Two MMUs inside each of the DSP1, and DSP2 subsystems: – DSP1 subsystem: DSP1_MMU0, and DSP1_MMU1 – DSP2 subsystem: DSP2_MMU0, and DSP2_MMU1 • Two MMUs inside each of the EVE1, EVE2, EVE3, and EVE4 subsystems: – EVE1 subsystem: EVE1_MMU0, and EVE1_MMU1 – EVE2 subsystem: EVE2_MMU0, and EVE2_MMU1 – EVE3 subsystem: EVE3_MMU0, and EVE3_MMU1 – EVE4 subsystem: EVE4_MMU0, and EVE4_MMU1 • Two MMUs inside each of the IPU1, and IPU2 subsystems: – L1 unicache MMU – IPU1_UNICACHE_MMU, and IPU2_UNICACHE_MMU – L2 MMU – IPU1_MMU, and IPU2_MMU
