Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence DONE! <<<---
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset.
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset.
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> DRA72x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL: Error while executing OnTargetConnect(): Target failed to read 0x4A002204
at (*((unsigned int *) 0x4A002204)&0xF0000000) [DRA72x_startup_common.gel:127]
at DRA72x_show_device_info() [DRA72x_startup_common.gel:104]
at DRA72x_target_connect_sequence() [DRA72x_startup_common.gel:40]
at OnTargetConnect()