fpga以相同的时间间隔向6678发数,发现6678响应的doorbell次数明显小于计算值,而且每次运行dsp响应的dorbell次数很随机,求大神指导!
另外,6678接收数据时,除了对srio初始化,大小端转换外还需要其他设置吗?谢谢!
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fpga以相同的时间间隔向6678发数,发现6678响应的doorbell次数明显小于计算值,而且每次运行dsp响应的dorbell次数很随机,求大神指导!
另外,6678接收数据时,除了对srio初始化,大小端转换外还需要其他设置吗?谢谢!
SRIO中断控制寄存器 中可以控制中断响应的间隔,你可以检查下如下寄存器配置,详情参考SRIO 用户手册的3.8.9.2节
The Interrupt Rate Control registers (INTDSTn_RATE_CNTL and
INTDST_RATE_DIS) are used to control the pace of interrupt generation on the
INTDST0 – INTDST15 interrupt lines.