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大家好,能大概讲诉一下chip-level interrupt controller 和 CorePac interrupt controller是啥关系,不是很清楚?谢谢了!我在用6678.
看一下下面的框图就很清楚CIC和corepac INTC之间的关系了。
http://processors.wiki.ti.com/index.php/Configuring_Interrupts_on_Keystone_Devices
chip level中断控制器可以理解成 芯片级中断,或者2级中断
CorePAC 中断是直接输送给CORE响应的,可以理解为1级中断, chip level中断的output可以是COREPAC interrupt的 input