原来是这样的：MCBSP1配成spi来收发，MCBSP2配成DSP模式接ak5702和wm8768来收发。现在MCBSP1只需用spi来发，在MCBSP1上再接个ak5702来收。应该怎么配置？谢谢。原来代码如下：
//16bit spi设置
MCBSP_Config mcbspCfg_daControl_16 =
{
MCBSP_SPCR1_RMK(MCBSP_SPCR1_DLB_OFF,
MCBSP_SPCR1_RJUST_LZF,
MCBSP_SPCR1_CLKSTP_DELAY,
MCBSP_SPCR1_DXENA_NA,
MCBSP_SPCR1_ABIS_DISABLE,
MCBSP_SPCR1_RINTM_RRDY,
MCBSP_SPCR1_RSYNCERR_NO,
MCBSP_SPCR1_RRST_DISABLE),
MCBSP_SPCR2_RMK(MCBSP_SPCR2_FREE_NO,
MCBSP_SPCR2_SOFT_NO,
MCBSP_SPCR2_FRST_RESET,
MCBSP_SPCR2_GRST_RESET,
MCBSP_SPCR2_XINTM_XRDY,
MCBSP_SPCR2_XSYNCERR_NO,
MCBSP_SPCR2_XRST_DISABLE),
MCBSP_RCR1_RMK( MCBSP_RCR1_RFRLEN1_OF(0),
MCBSP_RCR1_RWDLEN1_16BIT),
MCBSP_RCR2_RMK( MCBSP_RCR2_RPHASE_SINGLE,
MCBSP_RCR2_RFRLEN2_OF(0),
MCBSP_RCR2_RWDLEN2_8BIT,
MCBSP_RCR2_RCOMPAND_MSB,
MCBSP_RCR2_RFIG_YES,
MCBSP_RCR2_RDATDLY_1BIT),
MCBSP_XCR1_RMK( MCBSP_XCR1_XFRLEN1_OF(0),
MCBSP_XCR1_XWDLEN1_16BIT),
MCBSP_XCR2_RMK( MCBSP_XCR2_XPHASE_SINGLE,
MCBSP_XCR2_XFRLEN2_OF(0),
MCBSP_XCR2_XWDLEN2_8BIT,
MCBSP_XCR2_XCOMPAND_MSB,
MCBSP_XCR2_XFIG_YES,
MCBSP_XCR2_XDATDLY_1BIT),
MCBSP_SRGR1_RMK(MCBSP_SRGR1_FWID_OF(1),
MCBSP_SRGR1_CLKGDV_OF(240)),
MCBSP_SRGR2_RMK(MCBSP_SRGR2_GSYNC_FREE,
MCBSP_SRGR2_CLKSP_RISING,
MCBSP_SRGR2_CLKSM_INTERNAL,
MCBSP_SRGR2_FSGM_DXR2XSR,
MCBSP_SRGR2_FPER_OF(15)),
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK( MCBSP_PCR_IDLEEN_RESET,
MCBSP_PCR_XIOEN_SP,
MCBSP_PCR_RIOEN_SP,
MCBSP_PCR_FSXM_INTERNAL,
MCBSP_PCR_FSRM_EXTERNAL,
MCBSP_PCR_CLKXM_OUTPUT,
MCBSP_PCR_CLKRM_INPUT,
MCBSP_PCR_SCLKME_NO,
MCBSP_PCR_DXSTAT_0,
MCBSP_PCR_FSXP_ACTIVELOW,
MCBSP_PCR_FSRP_ACTIVEHIGH,
MCBSP_PCR_CLKXP_RISING,
MCBSP_PCR_CLKRP_FALLING),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};
//audio接口配置
MCBSP_Config mcbspCfg_audioData =
{
MCBSP_SPCR1_RMK(MCBSP_SPCR1_DLB_OFF, //DLB = 0,禁止自闭环方式
MCBSP_SPCR1_RJUST_LZF, //RJUST = 2左对齐低位补0
MCBSP_SPCR1_CLKSTP_DISABLE, //CLKSTP = 0 ，禁止clock stop模式
MCBSP_SPCR1_DXENA_NA,
MCBSP_SPCR1_ABIS_DISABLE,
MCBSP_SPCR1_RINTM_FRM,
MCBSP_SPCR1_RSYNCERR_NO,
MCBSP_SPCR1_RRST_DISABLE),
MCBSP_SPCR2_RMK(MCBSP_SPCR2_FREE_NO,
MCBSP_SPCR2_SOFT_NO,
MCBSP_SPCR2_FRST_RESET,
MCBSP_SPCR2_GRST_RESET,
MCBSP_SPCR2_XINTM_XRDY,
MCBSP_SPCR2_XSYNCERR_NO,
MCBSP_SPCR2_XRST_DISABLE),
MCBSP_RCR1_RMK( MCBSP_RCR1_RFRLEN1_OF(7), //RFRLEN1 = 7 ，接收帧长8个字节
MCBSP_RCR1_RWDLEN1_16BIT), //RWDLEN1 = 2 ，一个字节16bit
MCBSP_RCR2_RMK( MCBSP_RCR2_RPHASE_SINGLE, //RPHASE = 0 ,单相
MCBSP_RCR2_RFRLEN2_OF(0),
MCBSP_RCR2_RWDLEN2_8BIT,
MCBSP_RCR2_RCOMPAND_MSB,
MCBSP_RCR2_RFIG_YES,
MCBSP_RCR2_RDATDLY_0BIT), //RDATDLY = 0，接收帧0bit数据延迟
MCBSP_XCR1_RMK( MCBSP_XCR1_XFRLEN1_OF(7), //XFRLEN1 = 7，发送帧长8个字节
MCBSP_XCR1_XWDLEN1_16BIT), // XWDLEN1 = 2 ，一个字节16bit
MCBSP_XCR2_RMK( MCBSP_XCR2_XPHASE_SINGLE,
MCBSP_XCR2_XFRLEN2_OF(0),
MCBSP_XCR2_XWDLEN2_8BIT,
MCBSP_XCR2_XCOMPAND_MSB,
MCBSP_XCR2_XFIG_YES,
MCBSP_XCR2_XDATDLY_1BIT), //XDATDLY = 1 ，发送帧1bit延迟
MCBSP_SRGR1_RMK(MCBSP_SRGR1_FWID_OF(1),
MCBSP_SRGR1_CLKGDV_OF(1)),
MCBSP_SRGR2_RMK(MCBSP_SRGR2_GSYNC_FREE,
MCBSP_SRGR2_CLKSP_RISING,
MCBSP_SRGR2_CLKSM_CLKS,
MCBSP_SRGR2_FSGM_DXR2XSR,
MCBSP_SRGR2_FPER_OF(15)),
//MCBSP_MCR1_DEFAULT,
MCBSP_MCR1_RMK(0,0,0,0,1), //rmcm:receiver multiple channel mode
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK( MCBSP_PCR_IDLEEN_RESET, //IDLEEN = 0 ， 当PERIPH域空闲时，MCBSP保持使能
MCBSP_PCR_XIOEN_SP, //XIOEN = 0 ， CLKX,FSX,DX,CLKS脚是串口脚
MCBSP_PCR_RIOEN_SP, //RIOEN = 0 ， CLKR,FSR,DR,CLKS脚是串口脚
MCBSP_PCR_FSXM_EXTERNAL, // FSXM = 0 ， 发送帧同步脉冲由外部FSR脚提供
MCBSP_PCR_FSRM_EXTERNAL, // FSRM = 0 ， 接收帧同步脉冲由外部FSR脚提供
MCBSP_PCR_CLKXM_INPUT,
MCBSP_PCR_CLKRM_INPUT, //CLKRM = 0 , 接收器时钟由CLKR引脚获得
MCBSP_PCR_SCLKME_NO,
MCBSP_PCR_DXSTAT_0,
MCBSP_PCR_FSXP_ACTIVEHIGH, //FSXP = 0 , 发送帧脉冲高电平使能
MCBSP_PCR_FSRP_ACTIVEHIGH, //FSRP = 0 ，接收帧脉冲高电平使能
MCBSP_PCR_CLKXP_FALLING, //发送数据被驱动在CLKX的下降沿
//MCBSP_PCR_CLKRP_FALLING),
MCBSP_PCR_CLKRP_RISING), //MCBSP rising edge matched for AD
// MCBSP_RCERA_DEFAULT,
MCBSP_RCERA_RMK(0x00ff), //receiver TDM enable total 8 channels
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};
