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AM3352技术问题咨询

Other Parts Discussed in Thread: AM3352

Hi TI support,


目前有个触摸项目用到AM3352产品, 采用SPI启动,现在遇到下面两个问题,需要你帮忙支持一下。

 1XDS100V2.0仿真器 + AM3352Z芯片 + CCS 一直不能进入Debug模式,要进行Debug模式所必须的文件是哪些呢?(如:.gel文件)
 2
、我用flash烧写工具烧写了.bin文件,感觉一直没有加载,是我的文件下载错了吗?是不是下载一个_ti.bin文件?这个文件怎么产生呢?
       
看到StarterWare 02.00.00.06User Guide的说明,用/tools/ti_image/产生,但是一直报一个 Error opening input image file! 错。

  •  Dubug: 有没有建立xxx.ccxml文件

  • 现在解决了第二个问题,对于第一个问题(1XDS100V2.0仿真器 + AM3352Z芯片 + CCS 一直不能进入Debug模式,要进行Debug模式所必须的文件是哪些呢?(如:.gel文件)),我建立了xxx.ccxml文件得。感觉还差什么文件,一直连接不上处理器。

  • 打开ccxml文件,然后点击下面按钮,看看出现什么错误

  • 现在用的是CCS哪个版本?把您用的ccxml文件使用截图发出来看下。


  • 上面就是我的ccxml文件! 一直都连接不上板子,现在调程序很恼火,帮忙看看啥问题呢

  • 不是这种格式的ccxml文件,应该显示连接仿真器的。

  • 点击左下角的basic,再截图看看

  • 现在做的主要功能是,AM3352用的是AM335X_StarterWare_02_00_00_06 做一个串口1接收(用中断接收)和发送,现在能很好的发送,但是中断接收不了,我用PC上的串口工具发送数据给AM335X,程序就死掉了,感觉没有初始化中断向量表(void (*fnRAMVectors[NUM_INTERRUPTS])(void);  interrupt.c)。  调试了一天  没有发现问题,我附加了我的UART1的测序,还有CPU.c文件(是个汇编测序),希望能帮忙看看哪里不对。 谢谢!

    /**
     *  \file   cpu.c
     *
     *  \brief  CPU related definitions
     *
     *  This file contains the API definitions for configuring CPU
    */
    
    /*
    * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
    */
    /*
    *  Redistribution and use in source and binary forms, with or without
    *  modification, are permitted provided that the following conditions
    *  are met:
    *
    *    Redistributions of source code must retain the above copyright
    *    notice, this list of conditions and the following disclaimer.
    *
    *    Redistributions in binary form must reproduce the above copyright
    *    notice, this list of conditions and the following disclaimer in the
    *    documentation and/or other materials provided with the
    *    distribution.
    *
    *    Neither the name of Texas Instruments Incorporated nor the names of
    *    its contributors may be used to endorse or promote products derived
    *    from this software without specific prior written permission.
    *
    *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
    *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
    *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
    *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    *
    */
    
    
    #include "cpu.h"
    
    /*****************************************************************************
    **                   FUNCTION DEFINITIONS
    ******************************************************************************/
    /**
     * \brief     This API can be used to switch from user mode to privileged mode
     *            The priviledge mode will be system mode. System mode will share 
     *            the same resources as user mode, but with privileges.
     *
     * \param     None.
     *
     * \return    None.
     *
     * Note : All the access to system configuration which needs privileged access
     *        can be done after calling this API.
     **/
    void CPUSwitchToPrivilegedMode(void)
    {
        asm("    SWI   #458752");
    }
    
    /**
     * \brief     This API can be used to switch from any previleged mode of ARM to 
     *            user mode. After this API is called, the program will continue
     *            to operate in non-privileged mode, until any exception occurs.
     *            After the exception is serviced, execution will continue in user
     *            mode.
     *
     * \param     None.
     *
     * \return    None.
     *
     * Note : All the access to system configuration which needs privileged access
     *        shall be done before this API is called.
     **/
    void CPUSwitchToUserMode(void)
    {
        asm("    mrs     r0, CPSR\n\t"
            "    bic     r0, r0, #0x0F\n\t"
            "    orr     r0, r0, #0x10\n\t "
            "    msr     CPSR_c, r0");
    }
    
    /**
     * \brief     This API is called when the CPU is aborted or during execution
     *            of any undefined instruction. Both IRQ and FIQ will be disabled
     *            when the CPU gets an abort and calls this API. 
     *
     * \param     None.
     *
     * \return    None.
     *
     * Note : The user can perform error handling such as an immediate reset 
     *        inside this API if required.
     **/
    void CPUAbortHandler(void)
    {
        ;  /* Perform Nothing */
    }
    
    /*
    **
    ** Wrapper function for the IRQ status
    **
    */
    __asm("    .sect \".text:CPUIntStatus\"\n"
              "    .clink\n"
              "    .global CPUIntStatus\n"
              "CPUIntStatus:\n"
              "    mrs     r0, CPSR \n"
              "    and     r0, r0, #0xC0\n"
              "    bx      lr");
    
    
    /*
    **
    ** Wrapper function for the IRQ disable function
    **
    */
    void CPUirqd(void)
    {
        /* Disable IRQ in CPSR */
        asm("    mrs     r0, CPSR\n\t"
            "    orr     r0, r0, #0x80\n\t"
            "    msr     CPSR_c, r0");
    }
    
    /*
    **
    ** Wrapper function for the IRQ enable function
    **
    */
    void CPUirqe(void)
    {
        /* Enable IRQ in CPSR */
        asm("    mrs     r0, CPSR\n\t"
            "    bic     r0, r0, #0x80\n\t"
            "    msr     CPSR_c, r0");
    }
    
    /*
    **
    ** Wrapper function for the FIQ disable function
    **
    */
    void CPUfiqd(void)
    {
        /* Disable FIQ in CPSR */
        asm("    mrs     r0, CPSR\n\t"
            "    orr     r0, r0, #0x40\n\t"
            "    msr     CPSR_c, r0");
    }
    
    /*
    **
    ** Wrapper function for the FIQ enable function
    **
    */
    void CPUfiqe(void)
    {
        /* Enable FIQ in CPSR */
        asm("    mrs     r0, CPSR\n\t"
            "    bic     r0, r0, #0x40\n\t"
            "    msr     CPSR_c, r0");
    }
    
    /**************************** End Of File ************************************/
    


    /*
     * \file   uartEcho.c
     *
     * \brief  This is a sample application file which invokes some APIs
     *         from the UART/IrDA/CIR device abstraction library to perform
     *         configuration, transmission and reception operations.
     */
    
    /*
    * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
    */
    /*
    *  Redistribution and use in source and binary forms, with or without
    *  modification, are permitted provided that the following conditions
    *  are met:
    *
    *    Redistributions of source code must retain the above copyright
    *    notice, this list of conditions and the following disclaimer.
    *
    *    Redistributions in binary form must reproduce the above copyright
    *    notice, this list of conditions and the following disclaimer in the
    *    documentation and/or other materials provided with the
    *    distribution.
    *
    *    Neither the name of Texas Instruments Incorporated nor the names of
    *    its contributors may be used to endorse or promote products derived
    *    from this software without specific prior written permission.
    *
    *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
    *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
    *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
    *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    *
    */
    #include "hw_control_AM335x.h"
    #include "uart_irda_cir.h"
    #include "soc_AM335x.h"
    #include "interrupt.h"
    #include "uartStdio.h"
    #include "beaglebone.h"
    #include "hw_cm_wkup.h"
    #include "hw_cm_per.h"
    #include "hw_types.h"
    
    /******************************************************************************
    **              INTERNAL MACRO DEFINITIONS
    ******************************************************************************/
    #define UART_MODULE_INPUT_CLK     (48000000)
    
    /******************************************************************************
    **              INTERNAL FUNCTION PROTOTYPES
    ******************************************************************************/
    static void UartInterruptEnable(void);
    static void UART1AINTCConfigure(void);
    static void UartFIFOConfigure(unsigned int baseAdd);
    static void UartBaudRateSet(unsigned int baseAdd,unsigned int baudRate);
    static void UARTIsr(void);
    
    /******************************************************************************
    **              GLOBAL VARIABLE DEFINITIONS
    ******************************************************************************/
    unsigned char txArray[] = "StarterWare AM335X UART Interrupt application\r\n";
    
    /******************************************************************************
    **              FUNCTION DEFINITIONS
    ******************************************************************************/
    /**
     * \brief   This function selects the UART pins for use. The UART pins
     *          are multiplexed with pins of other peripherals in the SoC
     *
     * \param   instanceNum       The instance number of the UART to be used.
     *
     * \return  None.
     *
     * \note    This pin multiplexing depends on the profile in which the EVM
     *          is configured.
     */
    void UART1PinMuxSetup(unsigned int instanceNum)
    {
         if(1 == instanceNum)
              {
                   /* RXD */
                   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RXD(1)) =
                   (CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUTYPESEL |
                    CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RXACTIVE);
    
                   /* TXD */
                   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_TXD(1)) =
                    CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUTYPESEL;
              }
    }
    void UART1ModuleClkConfig(void)
    {
        /* Configuring L3 Interface Clocks. */
    
        /* Writing to MODULEMODE field of CM_PER_L3_CLKCTRL register. */
        HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) |=
              CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE;
    
        /* Waiting for MODULEMODE field to reflect the written value. */
        while(CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE !=
              (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
               CM_PER_L3_CLKCTRL_MODULEMODE));
    
        /* Writing to MODULEMODE field of CM_PER_L3_INSTR_CLKCTRL register. */
        HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) |=
              CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE;
    
        /* Waiting for MODULEMODE field to reflect the written value. */
        while(CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE !=
              (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
               CM_PER_L3_INSTR_CLKCTRL_MODULEMODE));
    
        /* Writing to CLKTRCTRL field of CM_PER_L3_CLKSTCTRL register. */
        HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) |=
              CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
    
        /* Waiting for CLKTRCTRL field to reflect the written value. */
        while(CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
              (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
               CM_PER_L3_CLKSTCTRL_CLKTRCTRL));
    
        /* Writing to CLKTRCTRL field of CM_PER_OCPWP_L3_CLKSTCTRL register. */
        HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) |=
              CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
    
        /*Waiting for CLKTRCTRL field to reflect the written value. */
        while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
              (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
               CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL));
    
        /* Writing to CLKTRCTRL field of CM_PER_L3S_CLKSTCTRL register. */
        HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) |=
              CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP;
    
        /*Waiting for CLKTRCTRL field to reflect the written value. */
        while(CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
              (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
               CM_PER_L3S_CLKSTCTRL_CLKTRCTRL));
    
        //2017.3.27  zhao
        HWREG(SOC_CM_PER_REGS + CM_PER_UART1_CLKCTRL) |=
        		CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE;
    
        while(CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE !=
        		(HWREG(SOC_CM_PER_REGS + CM_PER_UART1_CLKCTRL) &
        		CM_PER_UART1_CLKCTRL_MODULEMODE));
    
        /* Checking fields for necessary values.  */
    
        /* Waiting for IDLEST field in CM_PER_L3_CLKCTRL register to be set to 0x0. */
        while((CM_PER_L3_CLKCTRL_IDLEST_FUNC << CM_PER_L3_CLKCTRL_IDLEST_SHIFT)!=
              (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
               CM_PER_L3_CLKCTRL_IDLEST));
    
        /*
        ** Waiting for IDLEST field in CM_PER_L3_INSTR_CLKCTRL register to attain the
        ** desired value.
        */
        while((CM_PER_L3_INSTR_CLKCTRL_IDLEST_FUNC <<
               CM_PER_L3_INSTR_CLKCTRL_IDLEST_SHIFT)!=
              (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
               CM_PER_L3_INSTR_CLKCTRL_IDLEST));
    
        /*
        ** Waiting for CLKACTIVITY_L3_GCLK field in CM_PER_L3_CLKSTCTRL register to
        ** attain the desired value.
        */
        while(CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK !=
              (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
               CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));
    
        /*
        ** Waiting for CLKACTIVITY_OCPWP_L3_GCLK field in CM_PER_OCPWP_L3_CLKSTCTRL
        ** register to attain the desired value.
        */
        while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK !=
              (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
               CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK));
    
        /*
        ** Waiting for CLKACTIVITY_L3S_GCLK field in CM_PER_L3S_CLKSTCTRL register
        ** to attain the desired value.
        */
        while(CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK !=
              (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
              CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));
    
        //
    
        /* Configuring registers related to Wake-Up region. */
    }
    void UARTInit(unsigned int baseAdd,unsigned int baudRate)
    {
        /* Configuring the system clocks for UART1 instance. */
        UART1ModuleClkConfig();
    
        /* Performing the Pin Multiplexing for UART1 instance. */
        UART1PinMuxSetup(1);
    
        /* Performing a module reset. */
        UARTModuleReset(baseAdd);
    
        /* Performing FIFO configurations. */
        UartFIFOConfigure(baseAdd);
    
        /* Performing Baud Rate settings. */
        UartBaudRateSet(baseAdd,baudRate);
    
        /* Switching to Configuration Mode B. */
        UARTRegConfigModeEnable(baseAdd, UART_REG_CONFIG_MODE_B);
    
        /* Programming the Line Characteristics. */
        UARTLineCharacConfig(baseAdd,
                             (UART_FRAME_WORD_LENGTH_8 | UART_FRAME_NUM_STB_1),
                             UART_PARITY_NONE);
    
        /* Disabling write access to Divisor Latches. */
        UARTDivisorLatchDisable(baseAdd);
    
        /* Disabling Break Control. */
        UARTBreakCtl(baseAdd, UART_BREAK_COND_DISABLE);
    
        /* Switching to UART16x operating mode. */
        UARTOperatingModeSelect(baseAdd, UART16x_OPER_MODE);
    
        UARTCharPut(SOC_UART_1_REGS,'J');
        /* Performing Interrupt configurations. */
        UartInterruptEnable();
    
        UARTCharPut(SOC_UART_1_REGS,'E');
    }
    /*
    ** A wrapper function performing Interrupt configurations.
    */
    static void UartInterruptEnable(void)
    {
        /* Enabling IRQ in CPSR of ARM processor. */
        IntMasterIRQEnable();
    
        /* Configuring AINTC to receive UART0 interrupts. */
        UART1AINTCConfigure();
    
        /* Enabling the specified UART interrupts. */
        UARTIntEnable(SOC_UART_1_REGS, (UART_INT_LINE_STAT |
                                        UART_INT_RHR_CTI));
    }
    /*
    ** A wrapper function performing FIFO configurations.
    */
    
    static void UartFIFOConfigure(unsigned int baseAdd)
    {
        unsigned int fifoConfig = 0;
    
         //Setting the TX and RX FIFO Trigger levels as 1. No DMA enabled.
        fifoConfig = UART_FIFO_CONFIG(UART_TRIG_LVL_GRANULARITY_1,
                                      UART_TRIG_LVL_GRANULARITY_1,
                                      1,
                                      1,
                                      1,
                                      1,
                                      UART_DMA_EN_PATH_SCR,
                                      UART_DMA_MODE_1_ENABLE);
    
        // Configuring the FIFO settings.
        UARTFIFOConfig(baseAdd, fifoConfig);
    }
    /*
    ** A wrapper function performing Baud Rate settings.
    */
    
    static void UartBaudRateSet(unsigned int baseAdd,unsigned int baudRate)
    {
        unsigned int divisorValue = 0;
    
        /* Computing the Divisor Value. */
        divisorValue = UARTDivisorValCompute(UART_MODULE_INPUT_CLK,
        									 baudRate,
                                             UART16x_OPER_MODE,
                                             UART_MIR_OVERSAMPLING_RATE_42);
    
        /* Programming the Divisor Latches. */
        UARTDivisorLatchWrite(baseAdd, divisorValue);
    }
    /*
    ** Interrupt Service Routine for UART.
    */
    static void UARTIsr(void)
    {
        static unsigned int txStrLength = sizeof(txArray);
        static unsigned int count = 0;
        unsigned char rxByte = 0;
        unsigned int intId = 0;
    
        /* Checking ths source of UART interrupt. */
        intId = UARTIntIdentityGet(SOC_UART_1_REGS);
    
        switch(intId)
        {
            case UART_INTID_TX_THRES_REACH:
    
                if(0 != txStrLength)
                {
                    UARTCharPut(SOC_UART_1_REGS, txArray[count]);
                    txStrLength--;
                    count++;
                }
                else
                {
                    /* Disabling the THR interrupt. */
                    UARTIntDisable(SOC_UART_1_REGS, UART_INT_THR);
                }
    
            break;
    
            case UART_INTID_RX_THRES_REACH:
                rxByte = UARTCharGetNonBlocking(SOC_UART_1_REGS);
                UARTCharPutNonBlocking(SOC_UART_1_REGS, rxByte);
            break;
    
            case UART_INTID_RX_LINE_STAT_ERROR:
            case UART_INTID_CHAR_TIMEOUT:
                rxByte = UARTCharGetNonBlocking(SOC_UART_1_REGS);
            break;
    
            default:
            break;
        }
    }
    /*
    ** This function configures the AINTC to receive UART interrupts.
    */
    
    static void UART1AINTCConfigure(void)
    {
        /* Initializing the ARM Interrupt Controller. */
        IntAINTCInit();
    
        /* Registering the Interrupt Service Routine(ISR). */
        IntRegister(SYS_INT_UART1INT, UARTIsr);
    
        /* Setting the priority for the system interrupt in AINTC. */
        IntPrioritySet(SYS_INT_UART1INT, 0, AINTC_HOSTINT_ROUTE_IRQ);
    
        /* Enabling the system interrupt in AINTC. */
        IntSystemEnable(SYS_INT_UART1INT);
    }
    
    /******************************* End of file *********************************/
  • 第一个问题,参考附件中的pdf,关于CCS的章节部分,按照步骤做就可以,有具体问题了再反馈上来。

    第二个问题,_ti.bin只是在bin文件的基础上加了一个头,这个头内包含了loading的地址和当前的image的长度信息,这个是放在SD卡中进行启动或者app load的image。产生方法是用这个ti_image,但你在使用的时候要注意,bootloader和app的产生方式不一样的,是否有配置错命令?参考:

    http://processors.wiki.ti.com/index.php/AM335X_StarterWare_Booting_And_Flashing#Usage_of_ti_image_Tool

    PS: 一般来说,编我们的例程的话,我们在post build的相关设置中会自动调用相关的命令,生成_ti.bin的文件,直接用那个也可以。