增加了8个全局buf[64]后，cmd文件要改吗？感觉加上去后每次运行的结果都不一样。

原来的cmd代码

/**********************************************************/
/* */
/* LINKER command file for LEAD3 memory map */
/* */
/**********************************************************/

-stack 0x2000 /* Primary stack size */
-sysstack 0x1000 /* Secondary stack size */
-heap 0x2000 /* Heap area size */

-c /* C linking conventions: auto-init vars at runtime */
-u _Reset /* Force load of reset interrupt handler */

MEMORY
{
PAGE 0:

MMR : origin = 0000000h, length = 00000c0h
SPRAM : origin = 00000c0h, length = 0000040h
VECS : origin = 0000100h, length = 0000100h
DARAM0 : origin = 0000200h, length = 0003E00h
DARAM1 : origin = 0004000h, length = 000C000h

SARAM : origin = 0010000h, length = 0010000h

CE0 : origin = 0040000h, length = 03C0000h
CE1 : origin = 0400000h, length = 0400000h
CE2 : origin = 0800000h, length = 0400000h
CE3 : origin = 0C00000h, length = 03F0000h

PDROM : origin = 0FF0000h, length = 0FF00h
/* VECS : origin = 0ffff00h, length = 00100h */ /* reset vector */

PAGE 2: /* -------- 64K-word I/O Address Space -------- */

IOPORT (RWI) : origin = 0x000000, length = 0x020000
}

SECTIONS
{
.vectors : {} > VECS PAGE 0 /* interrupt vector table */
.cinit : {} > SARAM PAGE 0 /* Auto-initialization tables */
.pinit : {} > SARAM PAGE 0 /* Initialization fn tables */
.text : {} > SARAM PAGE 0 /* Code */
.switch : {} > SARAM PAGE 0 /* Switch statement tables */

.stack : {} > DARAM0 PAGE 0 /* Primary System Stack */
.sysstack: {} > DARAM0 PAGE 0 /* Secondary System Stack */
.sysheap : {} > DARAM0 PAGE 0 /* System Heap */
.sysmem : {} > DARAM1 PAGE 0 /* Dynamic memory (malloc) */
.cio : {} > DARAM1 PAGE 0 /* C I/O buffers */
.data : {} > DARAM1 PAGE 0 /* Initialized vars */
api_vect: {} > DARAM1 PAGE 0
api_lut : {} > DARAM1 PAGE 0
.bss : {} > DARAM1 PAGE 0 /* Global & static vars */
.const : {} > DARAM1 PAGE 0 /* Constant data */

.csldata : {} > DARAM0 PAGE 0
dmaMem : {} > DARAM0 PAGE 0

SDRAMBank0 : {} > CE0 PAGE 0
SDRAMBank1 : {} > CE1 PAGE 0
SDRAMBank2 : {} > CE2 PAGE 0
SDRAMBank3 : {} > CE3 PAGE 0

/* playWaveBufMem : {} > CE0 PAGE 0
recWaveBufMem : {} > CE1 PAGE 0 */

.ioport > IOPORT PAGE 2 /* Global & static ioport vars */
}