在DSP上同时使用I2C0与uPP,会导致I2C0的通信变得不可靠,有很大几率会失败,失败与成功的几率大概五五开,uPP倒是工作正常,请问是什么原因可能导致这个问题?
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请问,除了layout,是否还有可能是其他原因引起的?因为我关闭uPP只是reset了它,但是时钟和数据线的波形还是会产生的,并不会影响到我的i2c使用,请看我的代码。
#include <stdio.h>
#include "shared/protocol.h"
#include <stdlib.h>
//#include <stdint.h>
#include <uartStdio.h>
#include "evmOMAPL138.h"
#include "uart.h"
#include "soc_OMAPL138.h"
#include "hw_types.h"
#include "hw_syscfg0_OMAPL138.h"
#include <c674x/omapl138/interrupt.h>
#include <hw/soc_C6748.h>
#include <delay.h>
#include "fpga_upp.h"
#include "I2c_fpga.h"
#include "laser.h"
#define random(x) (rand()%x)
extern __SHM_RO data_type_ptr;
#define UPP_RX_LNCNT 1
/// S12443_CCD 2532 东芝的 TCD1254GFG 10128
#define UPP_RX_BCNT 2532
#define UPP_DMA_BCNT UPP_RX_BCNT*2
uint16_t recv_adc_buffer[UPP_RX_LNCNT*UPP_RX_BCNT];
uint8_t request_raw_data = 0;
//extern inline void dsp_delay(int ccc);
void ISR_ReceivedCMDFromARM(void);
void mydelay(unsigned long long t)
{
while(t--);
}
int main(void) {
uint8_t data[2048] = {0};
uint32_t i=655355;
uint32_t count = 0;
double res = 0.0;
unsigned int j = 3000;
U8 ret = 0;
// 全局中断初始化
IntDSPINTCInit();
IntGlobalEnable();
//初始化核间通信中断机制
DSP_CHIPSIG2_Init(ISR_ReceivedCMDFromARM);
SHM_DSP_Init();
UARTprintf("-------DSP has startup.------------\n");
//配置杂七杂八
FPGA_init_i2c();
fpga_writeRegister(1,0);
dsp_delay(1000);
fpga_writeRegister(1,7);
dsp_delay(1000);
fpga_writeRegister(2,50);
dsp_delay(1000);
UPP_PINMUX();
config_upp();
//laser_on(1);
//laser_on(0);
int frcnt;
frcnt=0;
int cc = 0;
int done = 0;
UARTprintf("--------write start------------\n");
while(1/*frcnt < 100000*/)
{
config_upp();//只要有调用了这个函数,i2c就会被影响, 这个函数只调用了void UPP_init(upp_config_t * config);
recv_adc_buffer[2531]=1;
upp_receive_fifo(recv_adc_buffer,UPP_RX_LNCNT,UPP_DMA_BCNT);
while(1)
{
if(recv_adc_buffer[2531]!=1 )
{
frcnt++;
if(*data_type_ptr == 0x01)//写入结果数据
{
res = frcnt;//recv_adc_buffer[10] * recv_adc_buffer[100] / 1000.0f;
ret = SHM_DSP_Write_Res((U8 *)&res, sizeof(double));
if(ret == SHM_SUCCEED)
{
done ++;
}
}
else if(*data_type_ptr == 0x02)//写入原始数据
{
if(request_raw_data == 1)
{
ret = SHM_DSP_Write_Raw((unsigned char *)recv_adc_buffer, RAW_BLOCK_SIZE);
request_raw_data = 0;
}
}
cc++;
break;
}
}
continue;
}
UARTprintf("--------write frame:%d, succeed:%d------------\n", frcnt, done);
}
//
void UPP_init(upp_config_t * config)
{
uint32_t i = 0;
//Provide power to uPP
//EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_RPI, PSC_ENABLE);
//reset uPP
SETBIT(UPP->UPPCR, UPP_UPPCR_SWRST);
for(i = 0; i < 200; i++){}; //wait 200 clock cycles for reset.
CLRBIT(UPP->UPPCR, UPP_UPPCR_SWRST);
//setup control registers
/* UPP->UPCTL=config->UPCTL.value;
UPP->UPICR=config->UPICR.value;
UPP->UPIVR=config->UPIVR.value;
UPP->UPTCR=config->UPTCR.value;
UPP->UPDLB=config->UPDLB.value;
UPP->UPIES=config->UPIES.value;
UPP->UPPCR=config->UPPCR.value;*/
//UPP->UPICR |= ((0x3<<19)|(0x3<<3)); //START signal is enabled.
}
支持时钟延展。TRM手册中有说明。
As a slave, the I2C peripheral does not generate the clock signal,
but it can hold I2Cx_SCL low while the intervention of the processor is required (RSFULL = 1 in
ICSTR) after data has been received.
Table 23-1. Operating Modes of the I2C Peripheral
http://www.ti.com/lit/ug/spruh77c/spruh77c.pdf