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利用NDK中client工程实现6678定制板与PC的网口通信,程序总跑不到main函数,该怎么解决?



请教各位大牛:

利用NDK中client工程实现DSP与PC的网口通信,在EVM板上可实现与PC正常的网口通信,但是移植到定制板上总是无法跑到main函数处;

利用GE工程对定制本的回环测试都通过了,然后利用按照如下修改测试:

GE_Test_Data_Path test_data_path= GE_TEST_DSP0_TO_DSP1;

Ethernet_Mode ethernet_mode = ETHERNET_AUTO_NEGOTIAT_SLAVE;

GE_Port_Connection port_connect[2]=
{

     GE_PORT_NO_CONNECT, //SGMII port 0

      GE_PORT_CABLE_CONNECT //SGMII port 1

};

不能完成测试,经查询寄存器状态发现port 0 的status reg 值为0x30,port 1的status reg 为0x31,由于我端口0没有用,仅使用了端口1,所以应该是按照上面的代码所示测试吧???

但是一旦我利用client工程发现port1的status reg 变为了0x30???不明白这点为什么会变??然后就一直停留在这个循环中:

do
{
CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);
} while (sgmiiStatus.bIsLinkUp != 1);

请问可以从哪些方面来考虑解决这个问题?

还要请问这个移植过程需要注意哪些地方?

谢谢!

 

  • 偶尔出现了下面情况,大多数经常卡在循环里

    JTAG ID= 0x1009e02f. This is C6678/TCI6608 device, version variant = 1.
    DEVSTAT= 0x00000001. little endian, No boot or EMIF16(NOR FLASH) or UART boot, PLL configuration implies the input clock for core is 50MHz.
    SmartReflex VID= 63, required core voltage= 1.104V.
    Die ID= 0x15005009, 0x04044cd8, 0x00000000, 0x4b9a0021
    Device speed grade = 1250MHz.
    Enable Exception handling...
    Initialize DSP main clock = 125.00MHz/1x8 = 1000MHz
    Initialize PASS PLL clock = 125.00MHz/5x42 = 1050.000MHz
    Initialize DDR speed = 125.00MHzx/3x32 = 1333.333MTS
    GE auto negotiation (slave) two DSPs test (DSP0 -> DSP1)...
    Unconnected SGMII0 port can only be used for internal loopback test
    Transferred 1472 bytes with 32002446 cycles, throughput= 0Mbps.
    STATSA.RxGoodFrames =32
    STATSA.RxOctets =2048
    STATSA.Frame64 =32
    STATSA.NetOctets =2048
    STATSB.TxGoodFrames =32
    STATSB.TxOctets =2048
    STATSB.Frame64 =32
    STATSB.NetOctets =2048
    SGMII0 Link Partner Advertised Ability SGMII port 0 FULLDUPLEX input signal from SGMII is low.
    SGMII1 Link Partner Advertised Ability 100Mbps Full Duplex
    SGMII port 1 GIG input signal from SGMII is low.
    MDIO ALIVE flag: 0xffffffff
    MDIO LINK flag: 0x00000002
    GE test complete.

  • EVM上验证ok,在你们自己做的板子上不ok的话,主要查一下main PLL,serdes PLL及DDR的配置,在STK例程中有根据不同的输入时钟计算配置例程。