FPGA通过SRIO向C6678发送数据,每次4096字节,共发送2048次,但是每次只能收到2036次DOORBELL,并且2036前的数据都是正确的,FPGA端抓取显示2036次后,ready信号就被拉低了。请问出现这种情况,原因可能有哪些呢?缓存区应该是够的
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请问您FPGA发送数据是采用的哪种 write 包? stream_write ,或者 write_post,或者 write_nopost形式?