【求助】关于AM335X GPMC WAIT功能的使用，读写等待时硬件卡死。

pc cldr

大家好，我手上有个beagle bone black 开发板，想通过 GPMC的与 FPGA进行 DMA读写，访问 FPGA内部寄存器时需要等待不同的时钟周期。

因此，我需要吧 GPMC配成带 WAIT的 NOR 同步模式，软件使用 AM335X_StarterWare 套件的驱动，以及 IAR开发工具编译裸机系统，JTAG下载运行。

程序跑起来后只要一读写 CS2的地址空间，AM335X就会卡死等待，JTAG都连不上了，必须要掉电重来。

我手动将FPGA 输出的 WAIT 线拉高拉低都不管用，只能将 GPMC_CONFIG Register （0x50000054）中的 WAIT0PINPOLARITY 改成 1h = WAIT0 active high，才不会卡死。将 GPMC_CONFIG1(2) 寄存器配置禁止 WAIT时，读写正常。

我现在觉得是 WAIT0 管脚没有配对，导致内部GPMC没有收到 WAIT0的回应。附初始化代码如下：请各位专家帮忙看下，哪里有问题？谢谢~

int main()
{
  BSPInit();
  UARTPuts("\n", -1);
  UARTPuts("*** cldr's am335x boot ***\n", -1);
  
  GPIO1ModuleClkConfig();
  GPIO0ModuleClkConfig();
  HWREG(SOC_CM_PER_REGS + CM_PER_GPIO2_CLKCTRL) |=
          CM_PER_GPIO2_CLKCTRL_MODULEMODE_ENABLE;
  HWREG(SOC_CM_PER_REGS + CM_PER_GPIO2_CLKCTRL) |=
          CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK;
  GPIOModuleEnable(SOC_GPIO_0_REGS);
  GPIOModuleReset(SOC_GPIO_0_REGS);
  GPIOModuleEnable(SOC_GPIO_1_REGS);
  GPIOModuleReset(SOC_GPIO_1_REGS);
  GPIOModuleEnable(SOC_GPIO_2_REGS);
  GPIOModuleReset(SOC_GPIO_2_REGS);
  
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(7)) = CONTROL_CONF_MUXMODE(0x7);
  GPIODirModeSet(SOC_GPIO_1_REGS, GPIO_LED_PIN_NUM, GPIO_DIR_OUTPUT);
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(3)) = CONTROL_CONF_MUXMODE(0x3);
  GPIO_PMUX_OFFADDR_VALUE(2, 0, PAD_FS_RXE_PU_PUPDE(7));
  GPIODirModeSet(SOC_GPIO_2_REGS, 0, GPIO_DIR_INPUT);  
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(1)) = CONTROL_CONF_MUXMODE(0x7);
  GPIODirModeSet(SOC_GPIO_1_REGS, 30, GPIO_DIR_OUTPUT);
  GPIOPinWrite(SOC_GPIO_1_REGS, 30, GPIO_PIN_LOW);      // Disable  eMMC, output  clk and command to 0.

  
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(3)) = PIN_MODE(0) | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE));
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(2)) = PIN_MODE(0) | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE));
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(1)) = PIN_MODE(0) | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE));
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(0)) = PIN_MODE(0) | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE));
  
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(7)) = PIN_MODE(0) | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL));
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(6)) = PIN_MODE(0) | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL));
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(5)) = PIN_MODE(0) | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL));
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(4)) = PIN_MODE(0) | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL));
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(3)) = PIN_MODE(0) | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL));
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) = PIN_MODE(0) | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL));
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(1)) = PIN_MODE(0) | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL));
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(0)) = PIN_MODE(0) | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL));
  
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WAIT0) = PIN_MODE(0) | PIN_PULL_UD_EN | PIN_RX_ACTIVE;
  
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(0)) = PIN_MODE(0) | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE));
  
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(2)) = PIN_MODE(0) | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE));
  
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CLK) = PIN_MODE(0) | ((PIN_PULL_UD_EN | PIN_RX_ACTIVE) & (~PIN_PULL_TYPE_SEL));
  
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_OEN_REN) = PIN_MODE(0) | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE));
  
  HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WEN) = PIN_MODE(0) | ((PIN_PULL_UD_EN) & (~PIN_PULL_TYPE_SEL & ~PIN_RX_ACTIVE));
  
  GPMCClkConfig();
  EDMAModuleClkConfig();
  HWREG(0x50000000 + 0x10) = 0x00000008;//SYSCONFIG
    HWREG(0x50000000 + 0x1C) = 0x00000000;
    HWREG(0x50000000 + 0x40) = 0x00001FF0;
    HWREG(0x50000000 + 0x44) = 0x00000000;
    HWREG(0x50000000 + 0x48) = 0x00000000;

    HWREG(0x50000000 + 0x50) = 0x00000002;//GPMC_CONFIG
    //CS0
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG1(0)) = 0x28000003;
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG2(0)) = 0x00040404;
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG3(0)) = 0x00000000;
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG4(0)) = 0x04040444;
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG5(0)) = 0x04040404;
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG6(0)) = 0x04040404;
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG7(0)) = 0x00000F41;

    //CS2
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG1(2)) = 0x28600003;
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG2(2)) = 0x00040404;
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG3(2)) = 0x00000000;
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG4(2)) = 0x04040444;
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG5(2)) = 0x04040404;
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG6(2)) = 0x04040404;
    HWREG(SOC_GPMC_0_REGS + GPMC_CONFIG7(2)) = 0x00000F42;
  
  shell();
  
}

8 年多前