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新购买的TMDSEVM6678L Rev.3A板，SRIO通讯好使，PORT OK不通过。
同样的测试环境，同样的OUT文件，加载在最初买的EVM6678L Rev1.0就可正常初始化通过。
不知道是何原因？
十万火急！
是不是卡在这呢？
/*---------wait all enabled ports OK-------------*/
//for(i=0; i<SRIO_MAX_PORT_NUM; i++)
for(i=0; i<2; i++)
{
if(srio_cfg->blockEn.bLogic_Port_EN[i])
while(0==(srioRegs->RIO_SP[i].RIO_SP_ERR_STAT&
CSL_SRIO_RIO_SP_ERR_STAT_PORT_OK_MASK));
}
请大侠们提出建议，
我使用的是SRIO_LoopbackDioIsrexampleproject工程，卡在：
while (CSL_SRIO_IsPortOk (hSrio, i) != TRUE);
解决了吗？我的也卡在这，用的是3.125G，4x，是不是不管FPGA程序有没有下载，只要DSP这边初始化正确就不会卡在这的
/* Assuming the link rate is 2500; program the PLL accordingly. */ CSL_BootCfgSetSRIOSERDESConfigPLL (0x251);//0x233
/* Configure the SRIO SERDES Receive Configuration. */CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x00440495);CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x00440495);CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x00440495);CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x00440495); /* Configure the SRIO SERDES Transmit Configuration. */ CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795); CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00080795); CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00080795); CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x00080795);
/* Configure the path mode for the ports. */// for(i = 0; i < 4; i++) CSL_SRIO_SetPLMPortPathControlMode (hSrio, 0, 4);
while (CSL_SRIO_IsPortOk (hSrio, 0) != TRUE); //4x just need to see port 0
程序就一直卡在这个循环里面，求助。
