各位大神好！我的是DM368的板子，然后是裸板跑的程序，自己配置的寄存器值。
然后我用的显示屏是320*240的，使用的DCLK是6.75Mhz。源时钟是27Mhz的。通过设定寄存器VENC_DCLKCTL = 0x0003;VENC_DCLKPTN0 = 0x0003;将频率降为了1/4。那么问题来了，我的背景窗口width设定了240*4=960，height设定为320，此时的背景窗口才刚好铺满整个屏幕。而OSDWIN0 的width = 480*320才刚好铺满整个屏幕，然后我在内存中组织数据时，也是要在其中每放一个像素点然后放一个空的dummy数据，再放第二个像素点，而且行上面也是间隔的加入空行数据才刚好能正常显示。我翻遍了VPBE的资料也没有找到合适的参考，请问哪位大神能帮忙解答一下？
以下是我的寄存器设定：
if ( ntsc_pal_mode == NTSC )
{
basep_x = 0;
basep_y = 0;
// width = 720;
// width = 790;
// height = 600;
// width = 960;
// height = 320;
width = 960;
height = 320;
}
else
{
basep_x = 132;
basep_y = 22;
width = 320;
height = 240;
}
/*
* Setup clocking / DACs
*/
// VDAC_CONFIG = 0x081141CF; // Take DACs out of power down mode
// VPSS_CLKCTL = 0x00000038; // Enable DAC and VENC clock, both at 27 MHz
// VPSS_VPBE_CLK_CTRL = 0x00000011; // Select enc_clk*1, turn on VPBE clk
// VPSS_CLKCTL = 0x0000000B; // Enable DAC and VENC clock, both at 27 MHz
VPSS_CLKCTL = 0x00000018; // Enable DAC and VENC clock, both at 27 MHz
VPSS_VPBE_CLK_CTRL = 0x00000019; // Select enc_clk*1, turn on VPBE clk
// VENC_CLKCTL = 0x00000011; // Enable venc & digital LCD clock DAC相关设置
/*
* Setup OSD
*/
// OSD_MODE = 0x000000fc; // Blackground color blue using clut in ROM0
OSD_MODE = 0x000000ff; // Blackground color blue using clut in ROM0
OSD_EXTMODE = 0;
// OSD_MODE = 0x000083fc;
OSD_OSDWIN0MD = 0; // Disable both osd windows and cursor window
OSD_OSDWIN1MD = 0;
OSD_RECTCUR = 0;
OSD_VIDWIN0OFST= ((video_buffer>>19)&0x1E00) | (width >> 4); //bit 12~9 store high 4bit 31~28
OSD_VIDWINADH = (video_buffer >> 21)&0x7F; //bit 6~0 store hight 7bit 27~21
OSD_VIDWIN0ADL = (video_buffer >> 5)&0xFFFF; //bit 15~0 stor 16bit 20~5
OSD_BASEPX =0;//137;// HPulse+91;
OSD_BASEPY =0;//38; //VPulse+36;
OSD_VIDWIN0XP = 100;//55;//一个值动两个像数
OSD_VIDWIN0YP = 100;//35;50
OSD_VIDWIN0XL = 240;
OSD_VIDWIN0YL = 100;
// OSD_VIDWINMD = 0x0201;//0x00000001; // Disable vwindow 1 and enable vwindow 0
OSD_VIDWINMD = 0;
/*liyan's test for bitmap*/
OSD_OSDWIN0OFST= ((video_buffer>>19)&0x1E00) | (width >> 4); //bit 12~9 store high 4bit 31~28
OSD_OSDWINADH = (video_buffer >> 21)&0x7F; //bit 6~0 store hight 7bit 27~21
OSD_OSDWIN0ADL = (video_buffer >> 5)&0xFFFF; //bit 15~0 stor 16bit 20~5
OSD_BASEPX =0;//137;// HPulse+91;
OSD_BASEPY =0;//38; //VPulse+36;
OSD_OSDWIN0XP = 0;//55;//一个值动两个像数
OSD_OSDWIN0YP = 8;//35;
OSD_OSDWIN0XL = 480;
OSD_OSDWIN0YL = 320;
// OSD_OSDWIN0MD = 0x000000C1;
OSD_OSDWIN0MD = 0x000060C1;
// Frame mode with no up-scaling
/*
* Setup VENC
*/
if ( ntsc_pal_mode == NTSC )
// VENC_VMOD = 0x00000003; // Standard NTSC interlaced output
VENC_VMOD = 0x00002013; // liyan change to No stardar video mode 130203
else
VENC_VMOD = 0x00002043; // Standard PAL interlaced output
VENC_HSPLS = HPulse; //HDW
VENC_VSPLS = VPulse; //VDW
// VENC_HINTVL = width-1; //PPLN
#if 1
VENC_HVALID = width; //LNH
VENC_HSTART = HSTART; //144
VENC_HINTVL = 1099;//4; //PPLN
//SPH
VENC_VVALID = height; //LNV
// VENC_VSTART = VSTART; //SLV
VENC_VSTART = VSTART; //SLV
VENC_VINTVL = 340; //2; //LPFR
#endif
#if 0
VENC_DCLKHSTT = HSTART;
VENC_DCLKHVLD = width;
VENC_DCLKVSTT = VSTART;
VENC_DCLKVVLD = height;
#endif
VENC_HSDLY = 0;//40;
VENC_VSDLY = 0;//40;
// VENC_CMPNT |= 0x8000;
VENC_YCCCTL = 0x10;
// VENC_VDPRO = colorbar_loopback_mode << 8;
VENC_VDPRO |= 0x200; // 100% Color bars
// VENC_VDPRO |= 0x40; // liyan change that YUV change to RGB
// VENC_VIOCTL |= 0x6000; //VCLK output enable
// VPSS_VPBE_CLK_CTRL = 0x00000011; // Select enc_clk*1, turn on VPBE clk
VENC_CLKCTL = 0x11;
VENC_SYNCCTL = 0x0F;
/*
* Choose Output mode
*/
if ( output_mode == COMPOSITE_OUT )
VENC_DACSEL = 0x00000000;
else if ( output_mode == SVIDEO_OUT )
VENC_DACSEL = 0x00004210;
VENC_VIOCTL = 0x2000; // Enable VCLK (VIDCTL)
// VENC_DCLKCTL = 0x0800; // Enable DCLK (DCLKCTL)
VENC_DCLKCTL = 0x0003;
VENC_DCLKPTN0 = 0x0003; // Set DCLK pattern (DCLKPTN0)
