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C6000 ,多核DDR3 LAYOUT问题



TI的工程师你们好:

              最近准备自己做C6657的板子,参考了文档DDR3 Design Requirements for KeyStone Devices,其中有DDR3关于地址,数据,命令,控制  分组的组内等长要求,有一点不明白,数据线组和地址线组之间有等长要求吗?