How to control EHRPWM via constant table ON pru

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#include <stdint.h>
#include <pru_cfg.h>
#include <pru_ctrl.h>
#include <sys_pwmss.h>//add by yoda
#include "resource_table_empty.h"

/* Mapping Constant Table (CT) registers to variables */
volatile far uint8_t CT_MCSPI0 __attribute__((cregister("MCSPI0", near), peripheral));

#ifndef PRU_SRAM
#define PRU_SRAM __far __attribute__((cregister("PRU_SHAREDMEM", near)))
#endif

/* NOTE:  Allocating shared_freq_x to PRU Shared Memory means that other PRU cores on
 *        the same subsystem must take care not to allocate data to that memory.
 *		  Users also cannot rely on where in shared memory these variables are placed
 *        so accessing them from another PRU core or from the ARM is an undefined behavior.
 */
PRU_SRAM volatile uint32_t shared_freq_1;
PRU_SRAM volatile uint32_t shared_freq_2;
PRU_SRAM volatile uint32_t shared_freq_3;

/* PRCM Registers */
#define CM_PER_BASE	((volatile uint8_t *)(0x44E00000))
#define SPI0_CLKCTRL  (0x4C)
#define ON (0x2)

#define MCSPI0_MODULCTRL (*((volatile uint32_t*)(&CT_MCSPI0 + 0x128)))

/* This is a char so that I can force access to R31.b0 for the host interrupt */
volatile register uint8_t __R31;

/* PRU-to-ARM interrupt */
#define PRU_ARM_INTERRUPT (19+16)

int main(void)
{
	uint32_t result;
	volatile uint8_t *ptr_cm;

	ptr_cm = CM_PER_BASE;

	/*****************************************************************/
	/* Access PRU peripherals using Constant Table & PRU header file */
	/*****************************************************************/

	/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
	CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;

	/* Read IEPCLK[OCP_EN] for IEP clock source */
	result = CT_CFG.IEPCLK_bit.OCP_EN;


	/*****************************************************************/
	/* Access SoC peripherals using Constant Table                   */
	/*****************************************************************/

	/* Access PRCM (without CT) to initialize McSPI0 clock */
	ptr_cm[SPI0_CLKCTRL] = ON;

	/* Read McSPI0_MODULCTRL (offset 0x128)*/
	result = MCSPI0_MODULCTRL;

	/* Toggle MCSPI0_MODULCTRL[MS] (offset 0x128, bit 2) */
	MCSPI0_MODULCTRL ^= 0x4;

	/* Reset MCSPI0_MODULCTRL[MS] to original value */
	MCSPI0_MODULCTRL = result;

	/*****************************************************************/
	/* Access PRU Shared RAM using Constant Table                    */
	/*****************************************************************/

	/* C28 defaults to 0x00000000, we need to set bits 23:8 to 0x0100 in order to have it point to 0x00010000	 */
	PRU0_CTRL.CTPPR0_bit.C28_POINTER = 0x0100;

	/* Define value of shared_freq_1 */
	shared_freq_1 = 1;

	/* Read PRU Shared RAM Freq_1 memory */
	if (shared_freq_1 == 1)
		shared_freq_2 = shared_freq_2 + 1;
	else
		shared_freq_2 = shared_freq_3;

	/*test PWM output*/
	PWMSS1.EPWM_TBPRD = 0x4B0;
	PWMSS1.EPWM_TBPHS = 0;
	PWMSS1.EPWM_TBCTL = 0;
	PWMSS1.EPWM_CMPCTL = 0;
	PWMSS1.EPWM_CMPA = 0x250;
	PWMSS1.EPWM_AQCTLA = 0x30;

	/* Halt PRU core */
	__halt();
}