GE以太网初始化问题

xinglin chen

Prodigy 200 points

利用K1_STK_v1.1中的例程GE工程在6678_EVM板上可以通过网口与PC进行数据传输，但是我在自己的板卡上跑这个程序时初始化不通过。在下面截图程序中出现了死循环。

原因是gpSGMII_regs[i]->STATUS_REG=0x30，所以while(0==(gpSGMII_regs[i]->STATUS_REG&CSL_CPSGMII_STATUS_REG_LINK_MASK));条件始终为真。

说明：自己的板卡使用的SGMII0, SERDES的参考时钟为250M。

程序修改部分：

其中模式设置如下：

Ethernet_Mode ethernet_mode = ETHERNET_AUTO_NEGOTIAT_SLAVE;

GE_Test_Data_Path test_data_path= GE_TEST_DSP0_TO_DSP1;

请问从SGMII1修改到SGMII0应该修改哪些地方？针对上面的问题求大神帮忙解答下。谢谢。

8 年多前

0 Shine 8 年多前

TI__Guru**** 357097 points

EVM板上的SRIO时钟是312.5MHz, 你用的是250MHz，需要修改，还有DDR不同的话，也要做修改。

doc文档里有讲。

4.4 Migrate the test to custom board

These examples are implemented based on TI’s EVM boards. In your real system, the DDR configuration may be changed according to your hardware design in the function C667x_EVM_DDR_Init() in “KeyStone_DDR_Init.c”.

DSP core PLL configuration may need be changed in “SRIO_test.c”:

//DSP core speed: 122.88*236/29= 999.9889655MHz

KeyStone_main_PLL_init(122.88, 236, 29);

SRIO reference clock speed may be changed with following code in main() function:

serdes_cfg.commonSetup.inputRefClock_MHz = 312.5;

To make your own configurations take effect, you must rebuild the project. Since CSL (Chip Support Library) are used by these projects, you may need change CSL including path in your system before you rebuild the project.