nandflash_pins_default: nandflash_pins_default {
pinctrl-single,pins = <
0x6c ( PIN_OUTPUT | MUX_MODE0 ) /* (V17) gpmc_a11.gpmc_a11 */
0x68 ( PIN_OUTPUT | MUX_MODE0 ) /* (T16) gpmc_a10.gpmc_a10 */
0x64 ( PIN_OUTPUT | MUX_MODE0 ) /* (U16) gpmc_a9.gpmc_a9 */
0x60 ( PIN_OUTPUT | MUX_MODE0 ) /* (V16) gpmc_a8.gpmc_a8 */
0x5c ( PIN_OUTPUT | MUX_MODE0 ) /* (T15) gpmc_a7.gpmc_a7 */
0x58 ( PIN_OUTPUT | MUX_MODE0 ) /* (U15) gpmc_a6.gpmc_a6 */
0x54 ( PIN_OUTPUT | MUX_MODE0 ) /* (V15) gpmc_a5.gpmc_a5 */
0x50 ( PIN_OUTPUT | MUX_MODE0 ) /* (R14) gpmc_a4.gpmc_a4 */
0x4c ( PIN_OUTPUT | MUX_MODE0 ) /* (T14) gpmc_a3.gpmc_a3 */
0x48 ( PIN_OUTPUT | MUX_MODE0 ) /* (U14) gpmc_a2.gpmc_a2 */
0x44 ( PIN_OUTPUT | MUX_MODE0 ) /* (V14) gpmc_a1.gpmc_a1 */
0x40 ( PIN_OUTPUT | MUX_MODE0 ) /* (R13) gpmc_a0.gpmc_a0 */
0x3c ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (U13) gpmc_ad15.gpmc_ad15 */
0x38 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (V13) gpmc_ad14.gpmc_ad14 */
0x34 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (R12) gpmc_ad13.gpmc_ad13 */
0x30 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (T12) gpmc_ad12.gpmc_ad12 */
0x2c ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (U12) gpmc_ad11.gpmc_ad11 */
0x28 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (T11) gpmc_ad10.gpmc_ad10 */
0x24 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (T10) gpmc_ad9.gpmc_ad9 */
0x20 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (U10) gpmc_ad8.gpmc_ad8 */
0x1c ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (T9) gpmc_ad7.gpmc_ad7 */
0x18 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (R9) gpmc_ad6.gpmc_ad6 */
0x14 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (V8) gpmc_ad5.gpmc_ad5 */
0x10 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (U8) gpmc_ad4.gpmc_ad4 */
0xc ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (T8) gpmc_ad3.gpmc_ad3 */
0x8 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (R8) gpmc_ad2.gpmc_ad2 */
0x4 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (V7) gpmc_ad1.gpmc_ad1 */
0x0 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (U7) gpmc_ad0.gpmc_ad0 */
0x70 ( PIN_INPUT_PULLUP | MUX_MODE0 ) /* (T17) gpmc_wait0.gpmc_wait0 */
0x74 ( PIN_INPUT_PULLUP | MUX_MODE7 ) /* (U17) gpmc_wpn.gpmc_wpn */
0x7c ( PIN_OUTPUT | MUX_MODE0 ) /* gpmc_csn0.gpmc_csn0 */
0x80 ( PIN_OUTPUT | MUX_MODE0 ) /* (U9) gpmc_csn1.gpmc_csn1 */
0x84 ( PIN_OUTPUT | MUX_MODE0 ) /* (V9) gpmc_csn2.gpmc_csn2 */
0x88 ( PIN_OUTPUT | MUX_MODE0 ) /* (T13) gpmc_csn3.gpmc_csn3 */
0x8c ( PIN_OUTPUT | MUX_MODE0 ) /* (V12) gpmc_clk.gpmc_clk */
0x90 ( PIN_OUTPUT | MUX_MODE0 ) /* (R7) gpmc_advn_ale.gpmc_advn_ale */
0x94 ( PIN_OUTPUT | MUX_MODE0 ) /* (T7) gpmc_oen_ren.gpmc_oen_ren */
0x98 ( PIN_OUTPUT | MUX_MODE0 ) /* (U6) gpmc_wen.gpmc_wen */
0x9c ( PIN_OUTPUT | MUX_MODE0 ) /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
&gpmc {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nandflash_pins_default>;
pinctrl-1 = <&nandflash_pins_sleep>;
ranges = <0 0 0x08000000 0x1000000>, /* CSn0: 16MB for NAND */
<1 0 0x01000000 0x1000000>; /* CSn1: 16MB for fpga */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 每个寄存器地址偏移4个字节*/
interrupt-parent = <&intc>;
interrupts = <100>;
ready-gpio = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000C0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001C0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x001E0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.rootfs";
reg = <0x00A00000 0x07600000>;
};
partition@10 {
label = "NAND.userdata";
reg = <0x08000000 0x08000000>;
};
};
fpga@1,0 {
compatible = "fpga";
status = "okay";
reg = <1 0 0x1000000>; //第一个是片选 第二个是相对该片选的基地址 ,第三个是length容量
nor-bus-width = <16>;
bank-width = <2>; /* GPMC_CONFIG1_DEVICESIZE(1) */
gpmc,sync-read; /* GPMC_CONFIG1_READTYPE_ASYNC */
gpmc,sync-write; /* GPMC_CONFIG1_WRITETYPE_ASYNC */
gpmc,clk-activation-ns = <0>; /* GPMC_CONFIG1_CLKACTIVATIONTIME(2) */
// gpmc,burst-length = <16>; /* GPMC_CONFIG1_PAGE_LEN(2) */
// gpmc,mux-add-data = <2>; /* GPMC_CONFIG1_MUXTYPE(2) */
gpmc,mux-add-data = <0>; /* GPMC_CONFIG1_MUXTYPE(2) */
gpmc,sync-clk-ps = <20000>; /* CONFIG2 */
/********************************************************************/
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <100>;
gpmc,cs-wr-off-ns = <40>;
gpmc,adv-on-ns = <0>; /* CONFIG3 */
gpmc,oe-on-ns = <20>;
gpmc,oe-off-ns = <100>;
gpmc,we-on-ns = <20>; /* CONFIG4 */
gpmc,we-off-ns = <40>;
gpmc,access-ns = <80>;
gpmc,rd-cycle-ns = <120>;
gpmc,wr-cycle-ns = <60>;
/*********************************************************************/
gpmc,adv-rd-off-ns = <20>;
gpmc,adv-wr-off-ns = <20>;
gpmc,page-burst-access-ns = <20>; /* CONFIG 5 */
gpmc,wr-access-ns = <40>; /* CONFIG 6 */
gpmc,wr-data-mux-bus-ns = <20>;
/*gpmc,bus-turnaround-ns = <40>;*/ /* CONFIG6:3:0 = 4 */
//gpmc,cycle2cycle-samecsen; /* CONFIG6:7 = 1 */
//gpmc,cycle2cycle-delay-ns = <20>; /* CONFIG6:11:8 = 4 */
/* not using dma engine yet, but we can get the channel number here */
};
};
问题有3:
1.这是dts里对fpga配置.整个配置对吗,在这里reg <1 0 0x1000000>这样写对吗,我把nand 和fpga的gpmc引脚配置在一起,这样处理对吗
2.dts里的时序配置如gpmc,oe-on-ns = <20>这些配置 和
#define STNOR_GPMC_CONFIG1 0x00001000
#define STNOR_GPMC_CONFIG2 0x0008080F
#define STNOR_GPMC_CONFIG3 0x001F1F0F
#define STNOR_GPMC_CONFIG4 0x010F010F
#define STNOR_GPMC_CONFIG5 0x00001F1F
#define STNOR_GPMC_CONFIG6 0x00000000
这里的时序配置有关吗 需要严格一致吗
3.编译后insmod fpga.ko 后通过printk打印报Failed request for GPMC mem for usrp_e错误.
原函数是
if ((gpmc_cs_request(GPMC_CS, SZ_4M, (unsigned long *)&mem_base) < 0)){
printk(KERN_ERR "Failed request for GPMC mem for usrp_e \n");
return -1;
}
这是什么情况造成的.望详细解答 万谢!
