开发板:Embest公司的sbc8600b,cpu为AM3358
问题:在sys/bios下跑enet_lwip,dual_mac程序时,两个网口都能够配置成功ip(不同网段的),link和netif通过检测都已经up了。但是实际上只有port1可用。port2能触发发包中断,但是网口传输灯不闪烁,外界也无法收到网口发送的数据包;从外界给port2发送数据包,网口数据传输灯闪烁,但触发不了收包中断。串口打印日志为:
88:c2:55:72:ab:55,mac
88:c2:55:72:ab:57,mac2
Acquiring IP Address for Port 1
PHY found at address 4 for Port 1 of Instance 0.
Performing Auto-Negotiation...
Auto-Negotiation Successful.
Transfer Mode : 100 Mbps Full Duplex.
PHY link verified for Port 1 of Instance 0.
Acquired IP Address : 192.168.2.10
Acquiring IP Address for Port 2
PHY found at address 6 for Port 2 of Instance 0.
Performing Auto-Negotiation...
Auto-Negotiation Successful.
Transfer Mode : 1000 Mbps.
PHY link verified for Port 2 of Instance 0.
Acquired IP Address : 192.168.1.11
在starterware下,同样的配置,两个网口都能正常工作。
sys/bios和裸机下的引脚复用,时钟使能,工作模式选择都使用的是下面三个函数
CPSWPinMuxSetup();
CPSWClkEnable();
EVMPortRGMIIModeSelect();
函数详细内容如下:
void CPSWPinMuxSetup(void)
{
//// rgmii2:
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(0)) = ///2;///tctl
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(1)) = /// 0x22;/// 2;////rctl
CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(2)) = /// 0x2;///td3
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(3)) = /// 0x2;///td2
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(4)) = /// 0x2;///td1
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(5)) = /// 0x2;///td0
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(6)) = /// 0x22;///tclk
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(7)) = ///0x22;//// 2;///rclk
CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(8)) = //// 0x22;///rd3
CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(9)) = //// 0x22;///rd2
CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(10)) = //// 0x22;////rd1
CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(11)) = //// 0x22;////rd0
CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
///rgmii1
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) =
CONTROL_CONF_MII1_COL_CONF_MII1_COL_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS) =
CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) =
CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXEN) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXDV) =
CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD3) =//0;
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD2) = // 0;
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD1) = // 0;
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD0) = // 0;
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXCLK) =
CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXCLK) =
CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD3) =
CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD2) =
CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD1) =
CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD0) =
CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE
| CPSW_RGMII_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK) =
CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_DATA) =
CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE
| CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL
| CPSW_MDIO_SEL_MODE;
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_CLK) =
CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL
| CPSW_MDIO_SEL_MODE;
}
void CPSWClkEnable(void)
{
HWREG(SOC_PRCM_REGS + CM_PER_CPGMAC0_CLKCTRL) =
CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_ENABLE;
while(0 != (HWREG(SOC_PRCM_REGS + CM_PER_CPGMAC0_CLKCTRL)
& CM_PER_CPGMAC0_CLKCTRL_IDLEST));
}
void EVMPortRGMIIModeSelect(void)
{
/* Select RGMII, Internal Delay mode */
HWREG(SOC_CONTROL_REGS + CONTROL_GMII_SEL) = 0x0A;
}
不知道sys/bios的哪些方面导致了这个问题的发生,希望能得到大家的帮助,谢谢!