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am335x +SYSBIOS+LWIP+DUAL MAC 只有port1可用

Other Parts Discussed in Thread: AM3358, SYSBIOS

开发板:Embest公司的sbc8600b,cpu为AM3358

问题:在sys/bios下跑enet_lwip,dual_mac程序时,两个网口都能够配置成功ip(不同网段的),link和netif通过检测都已经up了。但是实际上只有port1可用。port2能触发发包中断,但是网口传输灯不闪烁,外界也无法收到网口发送的数据包;从外界给port2发送数据包,网口数据传输灯闪烁,但触发不了收包中断。串口打印日志为:

88:c2:55:72:ab:55,mac
88:c2:55:72:ab:57,mac2
Acquiring IP Address for Port 1

PHY found at address 4 for  Port 1 of Instance 0.
Performing Auto-Negotiation...
Auto-Negotiation Successful.
Transfer Mode : 100 Mbps Full Duplex.
PHY link verified for Port 1 of Instance 0.
Acquired IP Address : 192.168.2.10
Acquiring IP Address for Port 2

PHY found at address 6 for  Port 2 of Instance 0.
Performing Auto-Negotiation...
Auto-Negotiation Successful.
Transfer Mode : 1000 Mbps.
PHY link verified for Port 2 of Instance 0.
Acquired IP Address : 192.168.1.11

在starterware下,同样的配置,两个网口都能正常工作。

sys/bios和裸机下的引脚复用,时钟使能,工作模式选择都使用的是下面三个函数

                  CPSWPinMuxSetup();
                   CPSWClkEnable();
                   EVMPortRGMIIModeSelect();

函数详细内容如下:

void CPSWPinMuxSetup(void)
{
 ////  rgmii2:

   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(0)) = ///2;///tctl
                      CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(1)) = /// 0x22;///  2;////rctl
                      CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
                      | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(2)) =   /// 0x2;///td3
                      CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(3)) =  /// 0x2;///td2
                      CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(4)) =   /// 0x2;///td1
                      CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(5)) =  /// 0x2;///td0
                      CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(6)) =   /// 0x22;///tclk
                      CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(7)) =  ///0x22;////  2;///rclk
                      CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
                      | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(8)) =  //// 0x22;///rd3
                      CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
                      | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(9)) =    //// 0x22;///rd2
                      CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
                      | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(10)) =   ////  0x22;////rd1
                      CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
                      | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(11)) = ////  0x22;////rd0
                      CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE
                      | CPSW_RGMII_SEL_MODE;

///rgmii1
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_COL) =
                     CONTROL_CONF_MII1_COL_CONF_MII1_COL_RXACTIVE
                     | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_CRS) =
                     CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE
                     | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXERR) =
                     CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE
                     | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXEN) =
                      CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXDV) =
                      CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RXACTIVE
                      | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD3) =//0;
                      CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD2) = // 0;
                      CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD1) = // 0;
                      CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXD0) = // 0;
                      CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_TXCLK) =
                      CPSW_RGMII_SEL_MODE;
   HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXCLK) =
                      CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RXACTIVE
                      | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD3) =
                      CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RXACTIVE
                      | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD2) =
                      CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RXACTIVE
                      | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD1) =  
                      CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE
                      | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MII1_RXD0) =  
                      CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE
                      | CPSW_RGMII_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_RMII1_REFCLK) =
                      CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_DATA) =
                      CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE
                      | CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL
                      | CPSW_MDIO_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_MDIO_CLK) =
                      CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL
                      | CPSW_MDIO_SEL_MODE;
}


void CPSWClkEnable(void)
{
    HWREG(SOC_PRCM_REGS + CM_PER_CPGMAC0_CLKCTRL) =
                      CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_ENABLE;

    while(0 != (HWREG(SOC_PRCM_REGS + CM_PER_CPGMAC0_CLKCTRL)
                & CM_PER_CPGMAC0_CLKCTRL_IDLEST));
}


void EVMPortRGMIIModeSelect(void)
{
    /* Select RGMII, Internal Delay mode */
    HWREG(SOC_CONTROL_REGS + CONTROL_GMII_SEL) = 0x0A;   
}

不知道sys/bios的哪些方面导致了这个问题的发生,希望能得到大家的帮助,谢谢!

  • sys/bios下跑enet_lwip,dual_mac 这个哪个版本的例程
  • Liu,
    你好!
    可算是等到你们的回复了。万分感谢!

    我的例程以“\AM335X_StarterWare_02_00_00_06 \examples\sbc8600\enet_lwip”下的文件和“\am335x_sysbios_ind_sdk_01.01.03.03\sdk\examples\enetLwip_sysbios”下的工程为参考建立的。
    sys/bios和starterware的工程中,lwip都用的是am335x_sysbios_ind_sdk_01.01.03.03文件夹下的lwip-1.4.0库,driver和platform等library都用的是买板子时光盘里面带的,裸机下没有任何问题。
    sys/bios版本为 6.46.5.55

    工程中从配置引脚复用到配置ip的代码为:
    CPSWPinMuxSetup();

    CPSWClkEnable();

    EVMPortRGMIIModeSelect();

    EVMMACAddrGet(0, lwipIfPort1.macArray);
    EVMMACAddrGet(1, lwipIfPort2.macArray);

    AintcCPSWIntrSetUp();

    UARTPuts("Acquiring IP Address for Port 1\n\r",-1);

    lwipIfPort1.instNum = 0;
    lwipIfPort1.slvPortNum = 1;///1;
    lwipIfPort1.ipAddr = STATIC_IP_ADDRESS_PORT1;
    lwipIfPort1.netMask = 0;
    lwipIfPort1.gwAddr = 0;
    lwipIfPort1.ipMode = IPADDR_USE_STATIC;

    ipAddr = lwIPInit(&lwipIfPort1);


    if(ipAddr)
    {

    UARTPuts("\n\rAcquired IP Address : ", -1);
    IpAddrDisplay(ipAddr);
    UARTPuts("\n\r", -1);
    //// UARTPuts("IP Address Assigned Successfully\n\r", -1);
    }
    else
    {

    UARTPuts("APort 1 IP Address Acquisition Failed.\n\r ", -1);
    }



    /////ip2


    UARTPuts("Acquiring IP Address for Port 2\n\r",-1);
    lwipIfPort2.instNum = 0;
    lwipIfPort2.slvPortNum = 2;///2;
    lwipIfPort2.ipAddr = STATIC_IP_ADDRESS_PORT2;
    lwipIfPort2.netMask = 0;
    lwipIfPort2.gwAddr = 0;
    lwipIfPort2.ipMode = IPADDR_USE_STATIC;

    ipAddr1 = lwIPInit(&lwipIfPort2);


    if(ipAddr1)
    {

    UARTPuts("\n\rAcquired IP Address : ", -1);
    IpAddrDisplay(ipAddr1);
    UARTPuts("\n\r", -1);
    /// UARTPuts("IP Address Assigned Successfully\n\r", -1);
    }
    else
    {

    UARTPuts("APort 1 IP Address Acquisition Failed.\n\r ", -1);
    }

    while(1)
    {

    }


    lwipopts.h文件配置为:

    #define CPSW_DUAL_MAC_MODE

    #define STATIC_IP_ADDRESS_PORT1 0xc0a8020A
    #define STATIC_IP_ADDRESS_PORT2 0xc0a8010B

    /*
    ** The below macro should be defined for using lwIP with cache. For cache
    ** enabling, pbuf pool shall be cache line aligned. This is done by using
    ** separate pool for each memory. The alignment of pbuf pool to cache line
    ** size is done in /ports/cpsw/include/arch/cc.h.
    */
    #define LWIP_CACHE_ENABLED

    #define SOC_CACHELINE_SIZE_BYTES 64 /* Number of bytes in
    a cache line */
    /*
    ** The timeout for DHCP completion. lwIP library will wait for DHCP
    ** completion for (LWIP_DHCP_TIMEOUT / 100) seconds.
    */
    #define LWIP_DHCP_TIMEOUT 500

    /*
    ** The number of times DHCP is attempted. Each time, the library will wait
    ** for (LWIP_DHCP_TIMEOUT / 100) seconds for DHCP completion.
    */
    #define NUM_DHCP_TRIES 5

    /*****************************************************************************
    ** lwIP SPECIFIC DEFINITIONS - To be used by lwIP stack
    *****************************************************************************/
    #define HOST_TMR_INTERVAL 0
    #define DYNAMIC_HTTP_HEADERS

    /*****************************************************************************
    ** Platform specific locking
    *****************************************************************************/
    #define SYS_LIGHTWEIGHT_PROT 1
    #define NO_SYS 0///0


    #define NO_SYS_NO_TIMERS 1

    /*****************************************************************************
    ** Memory Options
    *****************************************************************************/
    #define MEM_ALIGNMENT 4
    #define MEM_SIZE (128 * 1024) /* 128K */

    #define MEMP_NUM_PBUF 96
    #define MEMP_NUM_TCP_PCB 32
    #define PBUF_POOL_SIZE 210

    #ifdef LWIP_CACHE_ENABLED
    #define MEMP_SEPARATE_POOLS 1 /* We want the pbuf
    pool cache line
    aligned*/
    #endif

    /*****************************************************************************
    ** IP Options
    *****************************************************************************/
    #define IP_REASSEMBLY 0
    #define IP_FRAG 0

    /*****************************************************************************
    ** DHCP Options
    *****************************************************************************/
    #define LWIP_DHCP 1
    #define DHCP_DOES_ARP_CHECK 0

    /*****************************************************************************
    ** Auto IP Options
    *****************************************************************************/
    #define LWIP_AUTOIP 0
    #define LWIP_DHCP_AUTOIP_COOP ((LWIP_DHCP) && (LWIP_AUTOIP))

    /*****************************************************************************
    ** TCP Options
    *****************************************************************************/
    #define TCP_MSS 1500
    #define TCP_WND (8 * TCP_MSS)
    #define TCP_SND_BUF (8 * TCP_MSS)
    #define TCP_OVERSIZE TCP_MSS


    /*****************************************************************************
    ** TCP/IP Thread Options
    *****************************************************************************/
    #define TCPIP_THREAD_STACKSIZE 0x800 //0x2000//0x4000//0x8000
    #define TCPIP_MBOX_SIZE 1
    #define DEFAULT_RAW_RECVMBOX_SIZE 1
    #define DEFAULT_UDP_RECVMBOX_SIZE 1
    #define DEFAULT_TCP_RECVMBOX_SIZE 1
    #define DEFAULT_ACCEPTMBOX_SIZE 1



    /*****************************************************************************
    ** PBUF Options
    *****************************************************************************/
    #define PBUF_LINK_HLEN 14
    #define PBUF_POOL_BUFSIZE 1520 /* + size of struct pbuf
    shall be cache line
    aligned be enabled */
    #define ETH_PAD_SIZE 0
    #define LWIP_NETCONN 0 //0

    /*****************************************************************************
    ** Socket Options
    *****************************************************************************/
    #define LWIP_SOCKET 0 //0

    /*****************************************************************************
    ** Debugging options
    *****************************************************************************/
    #define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_OFF
    #define LWIP_DBG_TYPES_ON (LWIP_DBG_ON | LWIP_DBG_TRACE \
    |LWIP_DBG_STATE | LWIP_DBG_FRESH)

    #endif /* __LWIPOPTS_H__ */




    另外,最新的尝试结果:
    我发现即使不使用dual_mac_model在裸机下,通过两个网口都能访问到配置的ip。
    而sys/bios下port2相当于不能使用,不管用不用dual_mac model ,port2都ping不通,没有收包中断产生,发包有中断但根本发不出去。
    我除了用裸机的引脚复用外,还使用了processer sdk rtos里的am335x的pdk1.0.7中的board_init 进行引脚复用、时钟初始化,但跟使用自带驱动的效果是一样的,只有port1可用。
    但是我通过读取寄存器CONTROL_CONF_GPMC_A(0)到CONTROL_CONF_GPMC_A(11)的值,发现确实已经写成功,配置为了0x2或者0x22,即rgmii2。
    现在真的是不知道问题出在哪里了,应该是不是dual_mac_model的问题,就是不知道引脚复用还是什么原因导致了sys/bios下port2根本不能使用。

    希望能尽快得到你们的帮助,谢谢!
  • 建议:
    1. 先确认你的这个版本的相关例程是否支持到双网口的工能。因为AM335X_StarterWare_02_00_00_06这个版本已经很老了,TI已经不再继续维护了,建议你从安装目录下面找下release notes看看有没有说明,一般对于每个demo都有说明的,看看代码上有没有支持该功能。
    2. 从配置方面,建议在你尝试不能ping通的时候,用寄存器的访问直接查看对应的物理地址,这样就能确认是否是GMII_SEL,和PINMUX的配置问题导致的,特别要注意一些接收管教的receive enable是否被配置了,否则不能接收到物理信号的!
  • Liu,

    首先谢谢你的回复。

    但我还是有一些问题:
    1.我在裸机下完全可以运行双网口程序,只是移植到sys/bios下才出现的第二个网口不能用的问题,所以裸机的demo应该是支持双网口的。
    2.你所说的“用寄存器的访问直接查看对应的物理地址”这个具体怎么做呢,我直接通过HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_A(2))是访问到了寄存器的物理地址了吗?如果是的话,确实已经配置成功了啊.rgmii2的tctl ,rctl,tclk,rclk,td0~3,rd0~3寄存器,通过这种方法读到的值确实是配置的值啊。

    期待你们的回复,谢谢。