TI guys：
我在使用KeyStone_SRIO的例子在6670和6678的EVM板上进行自环测试，Digital Loopback都能够通过~但我观察到两块EVM板用的都是同一款三星DDR，每块DSP也都配备了4块这样的DDR，但Nyquist_EVM_DDR_Init和Shannon_EVM_DDR_Init这两个函数却差别非常大，引用如下：
6678中row size配置的是13bit
(DDR_ROW_SIZE_13_BIT<<CSL_EMIF4F_SDRAM_CONFIG_REG_ROWSIZE_SHIFT)
6670中row size 配置的是14bit
DR_ROW_SIZE_14_BIT<<CSL_EMIF4F_SDRAM_CONFIG_REG_ROWSIZE_SHIFT)
另外，6670中有关初始化leveling的代码与6678中有截然不同的配置
6670：
//initial vale for leveling
/*WRLVL_INIT_RATIO*/
boot_cfg_regs->DDR3_CONFIG_REG[2] = 0x0F;
boot_cfg_regs->DDR3_CONFIG_REG[3] = 0x0F;
boot_cfg_regs->DDR3_CONFIG_REG[4] = 0x20;
boot_cfg_regs->DDR3_CONFIG_REG[5] = 0x24;
boot_cfg_regs->DDR3_CONFIG_REG[6] = 0x33;
boot_cfg_regs->DDR3_CONFIG_REG[7] = 0x38;
boot_cfg_regs->DDR3_CONFIG_REG[8] = 0x21;
boot_cfg_regs->DDR3_CONFIG_REG[9] = 0x29;
boot_cfg_regs->DDR3_CONFIG_REG[10] = 0x0 ;
/*GTLVL_INIT_RATIO*/
boot_cfg_regs->DDR3_CONFIG_REG[14] = 0x7B;
boot_cfg_regs->DDR3_CONFIG_REG[15] = 0x7B;
boot_cfg_regs->DDR3_CONFIG_REG[16] = 0x8D;
boot_cfg_regs->DDR3_CONFIG_REG[17] = 0x89;
boot_cfg_regs->DDR3_CONFIG_REG[18] = 0xC0;
boot_cfg_regs->DDR3_CONFIG_REG[19] = 0xBC;
boot_cfg_regs->DDR3_CONFIG_REG[20] = 0xC3;
boot_cfg_regs->DDR3_CONFIG_REG[21] = 0xBB;
boot_cfg_regs->DDR3_CONFIG_REG[22] = 0x0 ;
6678：
//initial vale for leveling
/*GTLVL_INIT_RATIO*/
boot_cfg_regs->DDR3_CONFIG_REG[14] = 0xA1;
boot_cfg_regs->DDR3_CONFIG_REG[15] = 0x9E;
boot_cfg_regs->DDR3_CONFIG_REG[16] = 0xA7;
boot_cfg_regs->DDR3_CONFIG_REG[17] = 0xA9;
boot_cfg_regs->DDR3_CONFIG_REG[18] = 0xCA;
boot_cfg_regs->DDR3_CONFIG_REG[19] = 0xBE;
boot_cfg_regs->DDR3_CONFIG_REG[20] = 0xDD;
boot_cfg_regs->DDR3_CONFIG_REG[21] = 0xDD;
boot_cfg_regs->DDR3_CONFIG_REG[22] = 0xBA;
/*WRLVL_INIT_RATIO*/
boot_cfg_regs->DDR3_CONFIG_REG[2] = 0x20;
boot_cfg_regs->DDR3_CONFIG_REG[3] = 0x24;
boot_cfg_regs->DDR3_CONFIG_REG[4] = 0x3A;
boot_cfg_regs->DDR3_CONFIG_REG[5] = 0x38;
boot_cfg_regs->DDR3_CONFIG_REG[6] = 0x51;
boot_cfg_regs->DDR3_CONFIG_REG[7] = 0x5E;
boot_cfg_regs->DDR3_CONFIG_REG[8] = 0x5E;
boot_cfg_regs->DDR3_CONFIG_REG[9] = 0x5E;
boot_cfg_regs->DDR3_CONFIG_REG[10] = 0x44;
以及6670中多一段这样的代码：
/*the PHY_RESET is pulsed (0 -> 1 -> 0) to latch these
leveling configuration values into the PHY logic.*/
DDR_Regs->DDR_PHY_CTRL_1 &= ~(0x00008000);
DDR_Regs->DDR_PHY_CTRL_1 |= (0x00008000);
DDR_Regs->DDR_PHY_CTRL_1 &= ~(0x00008000);
6678同样有leveling,为什么没这样的配置？
之所以有这么多的问题，是因为当我把KeyStone_SRIO放在一块有双6670DSP，每块DSP只有两块同样型号三星DDR的板上跑单核digital loopback，DDR初始化不成功，DDR_Regs->STATUS这一部的三个状态全部为1，timeout~想请教一下为什么两块EVM板DDR初始化函数有这么大的区别，以及如果变成了2块DDR对应一块DSP，在一只时钟频率的基础上应该如何修改DDR初始化代码？谢谢
