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想问下，DDR3终端匹配电阻的端接耦合电容应该是接到VDD_DDR还是GND,看手册时钟线是端接到VDD_DDR，控制线和地址线尼，
另外，耦合电容的个数应该怎么分配，两个终端电阻用一个耦合电容可以吗，
有没有相关设计手册，谢谢
