C6748 L2RAM的使用

/****************************************************************************/
/* */
/* OMAPL138 及 DSP C6748 内存空间分配定义 */
/* */
/* 2014年05月16日 */
/* */
/****************************************************************************/

-stack 0x00400000
MEMORY
{

// DDR2 o = 0xC0600000 l = 0x40000000 /* 1GB DDR2 Data */
EntryPoint o = 0xC0600000 l = 0x00000800
// DDR2 o = 0xC0600800 l = 0x3FFFF800 /* 1GB DDR2 Data */
EMIFACS3 o = 0x62000000 l = 0x02000000 /* 32MB Async Data (CS3) */
DDR2 o = 0xC0600800 l = 0x02000000 /* 32MB DDR2 Data */
//DRAM org=0xC5000000 len=0x01000000 /* DDR */

DDR3 o = 0xC2600800 l = 0x00200000
DATA o = 0xC4000000 l = 0x0007D000 /* 8MB DDR2 分配给数据 */
/* PRU Memories */
PRU0_DATA_RAM : o = 0x01C30000, l = 0x00000200 // 512 B
PRU1_DATA_RAM : o = 0x01C32000, l = 0x00000200 // 512 B

PRU0_PROG_RAM : o = 0x01C38000, l = 0x00001000 // 4 KB
PRU1_PROG_RAM : o = 0x01C3C000, l = 0x00001000 // 4 KB


PRU_UART_A o = 0xC6001000 l = 0x00001400
PRU_UART_B o = 0xC6002400 l = 0x00001400

PRU_UART_A_1 o = 0xC6003800 l = 0x00001400
PRU_UART_B_1 o = 0xC6004C00 l = 0x00001400

norealtimefunction o = 0xC4800000 l = 0x00200000

}

SECTIONS
{


.text:_c_int00 > EntryPoint /* 可执行代码 C 程序入口点*/
.text > DDR2 /* 可执行代码 */
.stack > DDR2 /* 软件系统栈 */
// .bss > DDR2 /* 未初始化全局及静态变量 */
.cio > DDR2 /* C 输入输出缓存 */
.const > DDR2 /* 常量 */
.data > DDR2 /* 已初始化全局及静态变量 */
.switch > DDR2 /* 跳转表 */
.sysmem > DDR2 /* 动态内存分配区域 */
.far > DDR2 /* 远程全局及静态变量 */
.args > DDR2
.ppinfo > DDR2
.ppdata > DDR2

/* TI-ABI 或 COFF */
.pinit > DDR2 /* C++ 结构表 */
.cinit > DDR2 /* 初始化表 */

/* EABI */
.binit > DDR2
.init_array > DDR2
// .neardata > DDR2
.fardata > DDR2
// .rodata > DDR2
.c6xabi.exidx > DDR2
.c6xabi.extab > DDR2
.aisdata > DATA
GROUP: load > DDR2
{
.bss:
.neardata:
.rodata:
}

.SPIFPGA1 > DDR2
.SPIFPGA2 > DDR2

// .RXUPP > DDR2_36

.RXUPP > DDR2

.Adcp_Should_Out_Cache > DDR2 //2016.1.6 用来将一些实时性要求不高的数据，存放的结构体

.Pc_Cmd_For_Dsp > DDR2

.FLAG > DDR2

.REALCMDFORDSP > DDR2


.file_name>DDR2


.TF > DDR2

.Adcp_Timer_And_Rtc > DDR2

// .Adcp_Para_Temp_For_Uart > DDR2_19

.Adcp_Temp_Change > DDR2

// .Adcp_Real_Para_For_Calc > DDR2_21

.Pc_Para_For_Victor > DDR2

.Adcp_Parameter_For_Version1 > DDR2

.Carry_Only_Once > DDR2

.Flag_Active_Self_Check > DDR2

.Adcp_Work_Mode > DDR2

.Adcp_Rtc > DDR2

.Adcp_Dsp_With_Pc > DDR2 //DDR2//SHRAM//DDR6//SHRAM//DDR2_25

.Adcp_Parameter > DDR2

//.Adcp_I2c_Data > DDR2_20
.Adcp_I2c_Data > DDR2




.Dsp_To_Pc_Para_Modify>DDR2


.Adcp_Real_Para_For_Calc > DDR2


.Adcp_Result_V1>DDR2
.Adcp_Common_Uart_Count>DDR2
.Adcp_Parameter_User_Calc>DDR2
.Adcp_Sensor_Related_Calc_Temp>DDR2
.Four_Wave_Speed_Temp>DDR3//@@@@@@@@@@@@@@@@@@

.Adcp_Bottom_New_Data>DDR2
.Vxyz_And_Error>DDR2
.Echo_Intensity>DDR3//@@@@@@@@@@@@@@@@@@@@@
.Adcp_5k_Echo_Intensity>DDR3//@@@@@@@@@@@@@@@@@@@@@@@@@@@
.Beam_Array_Select>DDR3//@@@@@@@@@@@@@@@
.Bottom_Depth>DDR2
.Bottom_Depth_Side>DDR2
.Adcp_Vdz>DDR3//@@@@@@@@@@@@@@@@@@@@@@
.Intensity_And_Corr>DDR2
.Adcp_Output_V1>DDR2
.Adcp_Bottom_Trace_Data>DDR2
.Sensor_Data_Output>DDR2

.test_test>DDR3
.test_short>DDR3

.Adcp_Gps_Data_Temp>DDR2


.move1>DDR2
.move2>DDR2

.Config_Msg>DDR2

.Adcp_Output_Temp_V1>DDR2 //2015.12.27//DDR2 //2015.12.18



.wll_parameter>norealtimefunction
.SPI1PinMuxSetup>norealtimefunction
.Data_Init2>norealtimefunction

.Adcp_Calc_Test_Data_Init>norealtimefunction

.Adcp_Read_Baud_Rate>norealtimefunction

.Adcp_Write_Baud_Rate>norealtimefunction


.Adcp_Write_Work_State > norealtimefunction //XXXX
.Adcp_Read_Work_Mode > norealtimefunction //XXXX

.Adcp_Million_File_Name_PLUS>norealtimefunction

.Adcp_ParaAnalysis_For_Victor>norealtimefunction


.Upp_Reset_Fpga_Powerdown>norealtimefunction

.Adcp_Write_New_FileName > norealtimefunction


.UPPPinMuxSetup>norealtimefunction


.UPPEnable>norealtimefunction

.UPPInit>norealtimefunction

.UPPInterruptInit>norealtimefunction

.Upp_Sensor_Load>norealtimefunction


.Adcp_Uart_Transmit_Data>norealtimefunction

.Adcp_U_Disk_Related>DDR2 //2016.5.18
.aemif_mem > EMIFACS3, RUN_START(NANDStart)
.aisdata
{
. += 0x0007D000;
} load = DATA, FILL = 0x00000000, type = DSECT, START(EXTERNAL_RAM_START), END(EXTERNAL_RAM_END), SIZE(EXTERNAL_RAM_SIZE)



// .extram
// {
// . += 0x04000000;
// } load = DRAM, FILL=0x00000000, type=DSECT, START(EXTERNAL_RAM_START), END(EXTERNAL_RAM_END), SIZE(EXTERNAL_RAM_SIZE)//new 2017.6.9



.PRU0InstRAM:
{
. += 0x1000;
} load=PRU0_PROG_RAM, type=DSECT, FILL=0x00000000, START(PRU0_INST_START), SIZE(PRU0_INST_SIZE)

.PRU1InstRAM:
{
. += 0x1000;
} load=PRU1_PROG_RAM, type=DSECT, FILL=0x00000000, START(PRU1_INST_START), SIZE(PRU1_INST_SIZE)

.PRU0DataRAM
{
. += 0x200;
} load=PRU0_DATA_RAM, type=DSECT, FILL=0x00000000, START(PRU0_DATA_START), SIZE(PRU0_DATA_SIZE)

.PRU1DataRAM
{
. += 0x200;
} load=PRU1_DATA_RAM, type=DSECT, FILL=0x00000000, START(PRU1_DATA_START), SIZE(PRU1_DATA_SIZE)

.PRU_UART_1 > PRU_UART_A
.PRU_UART_2 > PRU_UART_B

.PRU_UART_1_1 > PRU_UART_A_1
.PRU_UART_2_1 > PRU_UART_B_1

}