AM1808 通过XDS100V2调试 DDR2 问题

你在ccs里面可以通过memory view正确的修改memory的值么？如果不可以，说明ddr还没有配置正确

有进展了,

我以前为测试DDR2时钟在gel中加了些测试，在GP6[14]输出DDR2时钟的，现在去掉了gel文件里的device_PLL0中

PLL0_OCSEL = 0x1E;
 PLL0_CKEN  = 0x02;
 PLL0_OSCDIV1 = 0x8000;

和device_PLL1中的

PLL1_OCSEL = 0x17;
PLL1_CKEN  = 0x02;
PLL1_OSCDIV1= 0x8000;

然后将DDRinit修改为

  PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_DDR2_MDDR,
                              0, PSC_MDCTL_NEXT_ENABLE);
    if (HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_VTPIO_CTL) &
                                                SYSCFG1_VTPIO_CTL_POWERDN)
    {
         ///Set IOPWRDN bit, powerdown enable mode
        HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_VTPIO_CTL) |=
                                          SYSCFG1_VTPIO_CTL_IOPWRDN;
         /// Clear POWERDN bit (enable VTP)
        //HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_VTPIO_CTL) |=
         //                                 SYSCFG1_VTPIO_CTL_POWERDN;
        HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_VTPIO_CTL) &=
                                                  ~SYSCFG1_VTPIO_CTL_POWERDN;

        HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_VTPIO_CTL) |=
                                                   SYSCFG1_VTPIO_CTL_CLKRZ;
         // Clear CLRZ bit
     HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_VTPIO_CTL) &=
                                          ~SYSCFG1_VTPIO_CTL_CLKRZ;
     // CLRZ bit should be low at least for 2ns
        //Delay(4);
        i = 100;
        while(i--);
        // Set CLRZ bit
    HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_VTPIO_CTL) |=
                                           SYSCFG1_VTPIO_CTL_CLKRZ;

     while (!(( HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_VTPIO_CTL) &
                                                         0x8000 ) >> 15));

        //Set Lock bit for static mode
 HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_VTPIO_CTL) |= SYSCFG1_VTPIO_CTL_LOCK;
        // set PWRSAVE bit to save Power
 HWREG(SOC_SYSCFG_1_REGS + SYSCFG1_VTPIO_CTL) |=
                                          SYSCFG1_VTPIO_CTL_PWRSAVE;
 // VTP Calibration ends
    }

    // Set BOOTUNLOCK
    HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDCR) |= DDR2_MDDR_SDCR_BOOTUNLOCK;

    // Set EXT_STRBEN and PWRDNEN bit of DDR PHY control register,
    //                               assign desired value to the RL bit

    //2012-12-4
    HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_DRPYC1R) =
                                                  DDR2_MDDR_DRPYC1R_EXT_STRBEN |
                                                  DDR2_MDDR_DRPYC1R_PWRDNEN    |
                                                  0x5;
    //2012-12-4

    HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDCR) = 0x00134832;

    HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDTIMR1) = 0x26922A09;

    HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDTIMR2) = 0x4414C722;//2012-12-4

    // CLEAR TIMINGUNLOCK
    //HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDCR) &= ~DDR2_MDDR_SDCR_BOOTUNLOCK;
    HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDCR) &= ~DDR2_MDDR_SDCR_TIMUNLOCK;
    //  IBANK_POS set to 0 so this register does not apply
    HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDCR2 ) = DDR2_MDDR_SDCR_IBANK_ONE;
    // SET the refreshing rate
    HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDRCR) = 0xC0000492;

    // SyncReset the Clock to SDRAM
    PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_DDR2_MDDR,
                              0,PSC_MDSTAT_STATE_SYNCRST);
    // Enable clock to SDRAM
    PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_DDR2_MDDR, 0,PSC_MDCTL_NEXT_ENABLE);
    // Disable Self refresh rate
    HWREG(SOC_DDR2_0_CTRL_REGS + DDR2_MDDR_SDRCR ) &= ~DDR2_SDRCR_CLEAR;
    HWREG(SOC_DDR2_0_CTRL_REGS +DDR2_MDDR_PBBPR)  = 0x20;

这样再操作100次循环 没有发生原来的现象，貌似解决了？？

如您所说，进入单步调试，在memory browser 里在0xc0000000 -0xc0000012处连续随机修改了值，然后单步读刚才修改地址处的值是和我写进去的值一样的

这能说明配置正确？

但是当我连续这样操作，如下

    i=0；

       while(1)
       {
       *(unsigned short* )0xC0000020  = 0xFFFF;
       *(unsigned short* )0xC0000024  = 0xFFFF;

        count = *(unsigned short* )0xC0000020;
        temp2 = *(unsigned short* )0xC0000024;

     if(count !=0xFFFF || temp2!=0xFFFF)
        {
         HWREG(SOC_GPIO_0_REGS + GPIO_SET_DATA(3)) = (1 << 14);//操作失败进入死循环点灯
         while(1)；
        }

        *(unsigned short* )0xC0000020  = 0;
        *(unsigned short* )0xC0000024  = 0;
        count = *(unsigned short* )0xC0000020;
        temp2 = *(unsigned short* )0xC0000024;

            if(count !=0 || temp2!=0)
        {
         HWREG(SOC_GPIO_0_REGS + GPIO_SET_DATA(3)) = (1 << 14);//操作失败进入死循环点灯
         while(1)；
        }

    i++；

       }

连续运行i不超过10万次操作就会操作失败进入死循环点灯,试了几次都是在4万多 ，3K多次就会失败，不知是否是我这样的读写方式不对，不可以对DDR2连续2个地址读写上千上万次？

问题有点多 请您耐心指教哦 谢谢！