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请问，如果FPGA通过SRIO端口向DSP的DDR里存数据，而此时DSP的程序运行又在调用DDR里的其他数据，那会不会出现DDR端口繁忙，导致SRIO传输过来的数据写入不到DDR中？？
您好 我也有这个问题，就是fpga向6678dsp的ddr写数据时，同时我读取ddr的其他数据就会使srio传输阻塞，请问您说的优先级具体怎么设置，谢谢
