请教一个关于DDR2配置相关的问题

在TRM DDR2/mDDR Memory Controller章节有详细的说明

15.2.1.3 DDR2/mDDR Memory Controller Internal Clock Domains

There are two clock domains within the DDR2/mDDR memory controller. The two clock domains are driven by VCLK and a divided-down by 2 version of 2X_CLK called MCLK. The command FIFO, write FIFO, and read FIFO described in Section 15.2.6 are all on the VCLK domain. From this, VCLK drives the interface to the peripheral bus. The MCLK domain consists of the DDR2/mDDR memory controller state machine and memory-mapped registers. This clock domain is clocked at the rate of the external DDR2/mDDR memory, 2X_CLK/2.

www.ti.com/.../spruh77c.pdf