TI8148 UBoot阶段应该如何配置HDMI？

是一样的，输出都是1080P 60帧；

配置参数如下：

ti810x_pll_config_hdmi(148500000);
    ti810x_hdmi_enable(148500000);
    ti810x_pll_config_dvo2(148500000);
    pll_write32(PLL_VIDEO2_PINMUX, 0);

    /*modeline "1920x1080" 148.50 1920 2008 2052 2200 1080 1084 1088 1125 +HSync +VSync */
    /*modeline "720x480" 27.000 720 736 798 858 480 489 495 525 -hsync -vsync*/
    /*modeline "640x480" 25.20 640 656 752 800 480 490 492 525 -HSync -VSync*/
    /** DVO1(HDMI) **/
    ti810x_vps_configure_venc(VPS_REG_BASE + 0x6000, 1920, 2008, 2052, 2200, 1080, 1084, 1089, 1125, 0, 0, 0,cmd);
    /** VENC_A(HDCOMP) **/
    ti810x_vps_configure_venc(VPS_REG_BASE + 0x8000, 1920, 2008, 2052, 2200, 1080, 1084, 1089, 1125, 0, 0, 0,cmd);
    /** DVO2 **/
    ti810x_vps_configure_venc(VPS_REG_BASE + 0xA000, 1920, 2008, 2052, 2200, 1080, 1084, 1089, 1125, 0, 0, 0,cmd);

你好 

我对比确认过了，时序确实是一模一样的。

我想对比一下在代码中有提到的寄存器，但是从sprugz8g这个文档中的寄存器介绍并不全，请问在哪可以看到这些寄存器的介绍呢？

关于标准的选择：BT601和BT709是否有影响呢，现在使用的是BT709，但是我不知道应该如何改成BT601

/**
 * Enable HDMI output.
 */
void ti810x_hdmi_enable(int freq)
{
    uint32_t temp, temp1;

    /* wrapper soft reset */
    temp = hdmi_read32(0x0010) ;
    temp1 = ((temp & 0xFFFFFFFE)| 0x1 );
    hdmi_write32(0x0300, temp1);
    temp = 0;
    udelay(10);

    /* configure HDMI PHY */
    /* 48 Mhz Clock input to HDMI ie SDIO clock output from PRCM */
    prcm_write32(0x15B0,0x2);

    // add by wx
    hdmi_setup_regs();

    /* Power on the phy from wrapper */
    hdmi_write32(0x0040, 0x8);

    while((hdmi_read32(0x0040) & 0x00000003) != 2);

    hdmi_write32(0x0040, 0x4A);
    while((hdmi_read32(0x0040) & 0x000000FF ) != 0x5A);

    hdmi_write32(0x0040, 0x8A);
    while((hdmi_read32(0x0040) & 0xFF) != 0xAA);

    /* Dummy read to PHY base to complete the SCP reset process HDMI_PHY_U_BAS */
    temp = hdmi_read32(0x0300);

    temp = hdmi_read32(0x0300);

    if(freq > 50000000)
    temp1 = ((temp & 0x3FFFFFFF)|(0x1 << 30));//0x40000000);
    else
    temp1 = ((temp & 0x3FFFFFFF)|(0x0 << 30));//0x40000000);
    hdmi_write32(0x0300, temp1);

    temp = hdmi_read32(0x030C) ;
    temp1 = ((temp & 0x000FFFFF)|0x85400000);
    hdmi_write32(0x030C, temp1);

    hdmi_write32(0x0304, 0xF0000000);

    udelay(10);

    /* cec clock divider config */
    temp = hdmi_read32(0x0070) ;
    temp1 = temp | 0x00000218;
    hdmi_write32(0x0070, temp1);

    /* wrapper debounce config */
    temp = hdmi_read32(0x0044) ;
    temp1 = temp | 0x00001414;
    hdmi_write32(0x0044, temp1);

    /* packing mode config */
    temp = hdmi_read32(0x0050) ;
    temp1 = temp | 0x105;
    hdmi_write32(0x0050, temp1);

    /* disable audio */
    hdmi_write32(0x0080, 0x0);

    /* release HDMI IP CORE reset and release power down of core */
    hdmi_write32(0x0414, 0x1);
    hdmi_write32(0x0424, 0x1);

    /* video action  config of hdmi */
    hdmi_write32(0x0524, 0x0);

    /* config input data bus width */
    hdmi_write32(0x0420, 0x7);

    /* configure AVI INFOFRAME */
    hdmi_write32(0x0528, 0x0);  // VID_MODE CONFIG
    hdmi_write32(0x04CC, 0x1);  // DATA ENABLE CNTRL
    hdmi_write32(0x0420, 0x37); // ENABLE VSYNC AND HSYNC
    hdmi_write32(0x04F8, 0x0);  // iadjust config to enable vsync
    hdmi_write32(0x0520, 0x10); // csc is bt709
    // enable change HDMI mode to DVI mode,
    // both DVI and HDMI monitor can works under DVI mode
    hdmi_write32(0x09BC, 0x20); // enable hdmi

    hdmi_write32(0x0608, 0x20); // tmds_ctrl
    hdmi_write32(0x0904, 0x0);  // disable n/cts of actrl
    hdmi_write32(0x0950, 0x0);  // disable audio
    hdmi_write32(0x0414, 0x0);  // keep audio  operation in reset state

    /* configure AVI INFOFRAME */
    hdmi_write32(0x0A00, 0x82);
    hdmi_write32(0x0A04, 0x2);
    hdmi_write32(0x0A08, 0xD);
    hdmi_write32(0x0A10, 0x1);
    hdmi_write32(0x0A14, 0xA0);
    hdmi_write32(0x0A1C, 0x8F);

    hdmi_write32(0x0538 , 0x3);  // DISABLE DEEP COLOR MODE IN DC PACKET
    hdmi_write32(0x09C0 , 0x10);
    hdmi_write32(0x09F8 , 0x3);  // ENABLE AND REPEAT AVI INFOFRAM TRANSMISSON
    hdmi_write32(0x09FC , 0xF);  // ENABLE AND REPEAT GENEERAL PACKET TRANSMISSION
}