C6657 利用SRIO与FPGA通信时,在FPGA不重新load程序而只是DSP重新load程序,多次试验后SRIO读写会有概率卡死在检查complete code上,请问专家出现这种情况怎么排查SRIO异常状态?保证每次load程序SRIO读写成功?
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