C645的PLL的倍频系数无法更改

PLLM寄存器的值改不了。代码用的官方的GEL文件里的初始化代码：
void init_PLL()
{
int i;
int PLLM_val = 20;
int PREDIV_val = 3;
int PLLDIV4_val = 3;
//int PREDIV_val = 1;
//int PLLDIV4_val = 4;
//int PREDIV_val = 1;
//int PLLDIV4_val = 3;
int PLLDIV5_val = 3;

//if (Get_Board_Rev == 0)
// PLLM_val = 25; // Old Rev, 40MHz CLKIN x 25 = 1GHz
//if (Get_Board_Rev == 1)
PLLM_val = 20; // Old Rev, 50MHz CLKIN x 20 = 1GHz
//if (Get_Board_Rev >= 2)
// PLLM_val = 24; // Old Rev, 50MHz CLKIN x 24 = 1.2GHz

if (PLLM_val > 0 && PLLM_val < 32)
{
if ( (PREDIV_val > 0) && (PREDIV_val < 33) )
{
/* In PLLCTL, write PLLENSRC = 0 (enable PLLEN bit).*/
*(int *)PLLCTL_1 &= ~(0x00000020);
/* In PLLCTL, write PLLEN = 0 (bypass mode).*/
*(int *)PLLCTL_1 &= ~(0x00000001);
/* Wait 4 cycles of the slowest of PLLOUT or reference clock source (CLKIN).*/
for (i=0 ; i<100 ; i++);
/*In PLLCTL, write PLLRST = 1 (PLL is reset).*/
*(int *)PLLCTL_1 |= 0x00000008;
/*If necessary, program PREDIV and PLLM.*/
*(int *)PLLM_1 = PLLM_val - 1;
*(int *)PREDIV_1 = (PREDIV_val - 1) | 0x8000; /* set PLLDIV0 */

/*If necessary, program PLLDIV1n. Note that you must apply the GO operation
to change these dividers to new ratios.*/

/* Check that the GOSTAT bit in PLLSTAT is cleared to show that no GO
operation is currently in progress.*/
while( (*(int *)PLLSTAT_1) & 0x00000001);


/* Program the RATIO field in PLLDIVn to the desired new divide-down rate.
If the RATIO field changed, the PLL controller will flag the change
in the corresponding bit of DCHANGE.*/
*(int *)PLLDIV4_1 = (PLLDIV4_val - 1) | 0x8000; /* set PLLDIV4 */
*(int *)PLLDIV5_1 = (PLLDIV5_val - 1) | 0x8000; /* set PLLDIV5 */

/* Set the GOSET bit in PLLCMD to initiate the GO operation to change
the divide values and align the SYSCLKs as programmed.*/
*(int *)PLLCMD_1 |= 0x00000001;

/* Read the GOSTAT bit in PLLSTAT to make sure the bit returns to 0
to indicate that the GO operation has completed.*/
while( (*(int *)PLLSTAT_1) & 0x00000001);

/* Wait for PLL to properly reset.(128 CLKIN1 cycles).*/
for (i=0 ; i<1000 ; i++);

/* In PLLCTL, write PLLRST = 0 to bring PLL out of reset.*/
*(int *)PLLCTL_1 &= ~(0x00000008);

/* Wait for PLL to lock (2000 CLKIN1 cycles). */
for (i=0 ; i<4000 ; i++);

/* In PLLCTL, write PLLEN = 1 to enable PLL mode. */
*(int *)PLLCTL_1 |= (0x00000001);

printf("PLL1 has been configured.\n");
}
else
{
printf("Pre-divider value must be between 1 and 32.\n","Output",2);
}
}
else
{
printf("Multiplier value must be between 1 and 32.\n","Output",2);
}
}