使用KeyStone_SRIO例程在6678le上进行测试，只修改了相应的模式其它部分代码未作改变：
1、SRIO_DIGITAL_LOOPBACK模式下发生如下数据错误：
[C66xx_0] SRIO path configuration 2xLaneAB_1xLaneC_1xLaneD
[C66xx_0] SWRITE from 0x12802200 to 0x13802200 through port 0, 16384 bytes, 20909 cycles, 6268 Mbps, completion code = 0
[C66xx_0] STREAM from 0x10802200 to 0x11806200 through port 2, 4096 bytes, 10663 cycles, 3073 Mbps, completion code = 3
[C66xx_0] data mismatch at unit 0, 0xa28 (at 0x10802200) != 0xa29 (at 0x11806200)
[C66xx_0] MESSAGE from 0x c002000 to 0x11802200 through port 3, 4096 bytes, 559214394 cycles, 0 Mbps, completion code = 2
[C66xx_0] data mismatch at unit 0, 0xa29 (at 0xc002000) != 0xa28 (at 0x11802200)
2、SRIO_SERDES_LOOPBACK模式下控制台结果如下：
[C66xx_0] SRIO_SERDES_LOOPBACK test start............................................
[C66xx_0] Initialize main PLL = x10/1
[C66xx_0] Initialize DDR PLL = x20/1
[C66xx_0] configure DDR at 666 MHz
[C66xx_0] SRIO link speed is 5.000Gbps
[C66xx_0] SRIO path configuration 1xLaneA
[C66xx_0] SWRITE from 0x10802200 to 0x10806200, 8 bytes, 4195 cycles, 15 Mbps, completion code = 0
[C66xx_0] data mismatch at unit 0, 0x1 (at 0x10802200) != 0xffffffff (at 0x10806200)
[C66xx_0] SWRITE from 0x10802200 to 0x10806200, 16 bytes, 4191 cycles, 30 Mbps, completion code = 0
[C66xx_0] data mismatch at unit 0, 0x2 (at 0x10802200) != 0xffffffff (at 0x10806200)
[C66xx_0] SWRITE from 0x10802200 to 0x10806200, 32 bytes, 4464 cycles, 57 Mbps, completion code = 0
[C66xx_0] data mismatch at unit 0, 0x3 (at 0x10802200) != 0xffffffff (at 0x10806200)
[C66xx_0] SWRITE from 0x10802200 to 0x10806200, 64 bytes, 4761 cycles, 107 Mbps, completion code = 0
[C66xx_0] data mismatch at unit 0, 0x4 (at 0x10802200) != 0xffffffff (at 0x10806200)
[C66xx_0] SWRITE from 0x10802200 to 0x10806200, 128 bytes, 5154 cycles, 198 Mbps, completion code = 0
[C66xx_0] data mismatch at unit 0, 0x5 (at 0x10802200) != 0xffffffff (at 0x10806200)
程序停留在
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请问如何进一步修改呢，论坛中相关问题都已经浏览一遍，没有找到实质性的帮助，请专家指导。
