在配置SPI nor flash boot时发现SPI时钟不对导致flash读取不稳定，定位发现同样的输入时钟，我用×32/4和×16/2两种配置PLL，前者输出时钟不对，后者对。
看文档sprugv2i.pdf 《KeyStone Architecture Phase-Locked Loop (PLL) User's Guide》，里面有Table 4-3. PLL Secondary Control Register (SECCTL) Field Descriptions
提到：
Output Divider ratio bits.
For Keystone I devices,
1h = Divide frequency by 2 (default)
for Keystone II devices,
0h = Divide frequency by 1
1h-Fh = Divide frequency by 2, to divide frequency by 16 (only even values)
但是没有明确说Keystone I devices只能除2
请问有没有哪个文档明确说明Keystone I 不支持2以上分频操作？
