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AM437X数据手册上仅介绍了DDR3采用fly-by拓扑结构时走线的公差控制。当采用T型结构时，地址线、命令线走线公差是多少？
链接中没有说明具体的走线约束,在采用T型结构时按照手册上推荐的只采用A1和A2，AS的走线长度和公差进行约束，这样是否可以？
