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When the timeout event occurs, the Watchdog Timer could reset the entire processor depending on how
the watchdog reset (WDRST) bit located in the timer control register (TIMERCTL) within the System
Module is programmed. If the WDRST bit is set to 1, then a Watchdog Timer event causes a device reset.
If the WDRST bit is cleared to 0, then a Watchdog Timer event does not cause a device reset.
