TI工程师你好，
我在使用STM_PCIE例程时遇到了一些问题。
按照KeyStone 1 PCIE Self Test Kit User’s Guide，将程序分别运行在DSP0 0core和DSP1 1core。打印如下信息。
[C66xx_0] JTAG ID= 0x1009e02f. This is C6678/TCI6608 device, version variant = 1.
DEVSTAT= 0x00012e0d. little endian, SPI boot, PLL configuration implies the input clock for core is bypassed.
SmartReflex VID= 55, required core voltage= 1.052V.
Die ID= 0x0b014005, 0x04045e43, 0x00000000, 0x167a0021
Device speed grade = 1000MHz.
Enable Exception handling...
Initialize DSP main clock = 100.00MHz/1x10 = 1000MHz
Initialize DDR speed = 100.00MHzx/1x10 = 1000.000MTS
PCIE normal and RC mode at 5.0GHz, should be running on core0.
PCIE start link training...
PCIE link training is finished.
External exception happened. MEXPFLAG[3]=0x4004000.
Event 110: MDMAERREVT XMC VBUSM error event
MDMA read status error detected
XID (Transaction ID)= 3
Timeout error
Event 122: DMC_CMPA CPU memory protection fault for L1D (and other memory read finally goes through the L1D controller)
memory protection exception caused by local access at 0x21803050
Supervisor Read violation
NRP=0xc009f24, NTSR=0x1800d, IRP=0x0, ITSR=0x0, TSCH= 0x0, TSCL= 0x3b8535b
B3=0xc00bff8, A4=0x21803050, B4= 0x1000054, B14= 0x8023c8, B15= 0x8011a0
Exception happened at a place can not safely return!
EP那边一直停留在PCIE link training is finished.
代码似乎是在运行下面这个函数的时候出问题的。
KeyStone_PCIE_RC_MSI_allocate((PCIE_MSI_Regs *)&gpPCIE_remote_EP_regs->MSI_CAP,
PCIE_RC_BAR0_ADDRESS+((Uint32)&gpPCIE_app_regs->MSI_IRQ)-(Uint32)gpPCIE_app_regs);
不知道是什么原因。
希望能帮助解答一下。
衷心感谢
