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仿真器连接不上

Other Parts Discussed in Thread: TPS650250

想问一下,自己作的6748板子,参照 TI6748 LCD原理图,dsp电源没有问题,仿真器连接不上,测量复位引脚是1.1V,现在找不到原因

  • 复位部分是参考原理图设计的吗?请问此时VDD电压多少呢?如果vdd是3.3v的话,reset高电压也应该为3.3v。

  • 谢谢您的回复,DVDD18接1.8V ,DVDD3318接3.3V.复位部分电路现在都拆了,电压有时是1.1 V,有时就变成0.8V,我想问下dsp6748正常工作的话功耗是多大,我dsp 供5V电压,电流,147mA,这能说明DSP运行了吗?
  • 量到JTAG口的EMU0和EMU1是2.68V
  • #1.共有几块板子,都有这个问题吗?

    #2. 电源没问题,是指电压没问题吧,上时时序符合要求吗? 1.1V->1.8V->3.3V. 

    #3. 间接判断一下DSP是否工作了: 将启动模式改到UART boot, 从串口看是否能收到BOOTME输出.

    RESET是输入脚,外部可以加一个上拉电阻. 通过将RESET手动捅一下GND来手动复位DSP.

  • 上电顺序没有问题,dsp 启动应该也没问题,JTAG连接到板卡后,RTST引脚没有被驱动成高电平

  • 看清楚我的问题,按顺序回答。

  • 1.共有5块板子,测了三块都有这个问题

    2.电源上电顺序没有问题,用的TPS650250电源芯片1.3->1.8->3.3

    3.间接判断DSP工作:用UART2启动模式串口的收发如下

    RESET外部上拉到3.3V后JTAG口的电压都正常,但是还是连接不上仿真器,提示如下错误:

    [Start]

    Execute the command:

    %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

    [Result]


    -----[Print the board config pathname(s)]------------------------------------

    C:\Users\Administrator\AppData\Local\.TI\
    2526794187\0\0\BrdDat\testBoard.dat

    -----[Print the reset-command software log-file]-----------------------------

    This utility has selected a 100- or 510-class product.
    This utility will load the adapter 'jioserdesusb.dll'.
    The library build date was 'Aug 20 2013'.
    The library build time was '22:56:19'.
    The library package version is '5.1.232.0'.
    The library component version is '35.34.40.0'.
    The controller does not use a programmable FPGA.
    The controller has a version number of '4' (0x00000004).
    The controller has an insertion length of '0' (0x00000000).
    This utility will attempt to reset the controller.
    This utility has successfully reset the controller.

    -----[Print the reset-command hardware log-file]-----------------------------

    The scan-path will be reset by toggling the JTAG TRST signal.
    The controller is the FTDI FT2232 with USB interface.
    The link from controller to target is direct (without cable).
    The software is configured for FTDI FT2232 features.
    The controller cannot monitor the value on the EMU[0] pin.
    The controller cannot monitor the value on the EMU[1] pin.
    The controller cannot control the timing on output pins.
    The controller cannot control the timing on input pins.
    The scan-path link-delay has been set to exactly '0' (0x0000).

    -----[The log-file for the JTAG TCLK output generated from the PLL]----------

    There is no hardware for programming the JTAG TCLK frequency.

    -----[Measure the source and frequency of the final JTAG TCLKR input]--------

    There is no hardware for measuring the JTAG TCLK frequency.

    -----[Perform the standard path-length test on the JTAG IR and DR]-----------

    This path-length test uses blocks of 512 32-bit words.

    The test for the JTAG IR instruction path-length failed.
    The JTAG IR instruction scan-path is stuck-at-ones.

    The test for the JTAG DR bypass path-length failed.
    The JTAG DR bypass scan-path is stuck-at-ones.

    -----[Perform the Integrity scan-test on the JTAG IR]------------------------

    This test will use blocks of 512 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Test 2 Word 0: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 1: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 2: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 3: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 4: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 5: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 6: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 7: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    The details of the first 8 errors have been provided.
    The utility will now report only the count of failed tests.
    Scan tests: 2, skipped: 0, failed: 1
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 2
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 3
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 4
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 5
    Some of the values were corrupted - 83.3 percent.

    The JTAG IR Integrity scan-test has failed.

    -----[Perform the Integrity scan-test on the JTAG DR]------------------------

    This test will use blocks of 512 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Test 2 Word 0: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 1: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 2: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 3: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 4: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 5: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 6: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    Test 2 Word 7: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
    The details of the first 8 errors have been provided.
    The utility will now report only the count of failed tests.
    Scan tests: 2, skipped: 0, failed: 1
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 2
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 3
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 4
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 5
    Some of the values were corrupted - 83.3 percent.

    The JTAG DR Integrity scan-test has failed.

    [End]

  • 55 AA是什么?你发送的,还是接收到从板子上发出来的?

  • 这时用镊子捅一下GND做一下手动复位,看UART是否有输出。如果没有,说明芯片没有工作。前提是boot mode确实配成了UART.

    如果上面做了还是串口输出,则是硬件问题了。时钟,电源,复位都没问题的话,就可能是焊接有问题了。用热风枪吹一吹,或者用手压一压芯片试试。

  • 按您说的捅了复位按钮,串口的输出如图,这样是不是说明芯片工作了?

  • 正确情况是收到: BOOTME, 每复位一次, 发一个BOOTME出来.

  •  刚刚是我配置错了,是16进制显示,可以收到BOOTME信息

  • 这么说来芯片是正常工作了。这时还连不上吗?那么就看JTAG电路上有没有什么问题呢?这部分相关电路贴上来看一下

  • RTCK接在哪?接在PIN K17吗?

    在有bootme输出的情况下还是连不上吗?

  • 嗯嗯 ,还是连接不上

  • 连接时报什么错?

    偏向于是焊接问题了。

    测试或者连接时,看RTCK上有时钟回来吗?

    TRST没有接到RESET吧.

    同时,你前面提到的RESET一直为低,这也是说不通的,这个问题是不是复位芯片或者电路有问题?

  • 1 报的错误Start]

    Execute the command:

    %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

    [Result]

    -----[Print the board config pathname(s)]------------------------------------

    C:\Users\Administrator\AppData\Local\.TI\

       2526794187\0\0\BrdDat\testBoard.dat

    -----[Print the reset-command software log-file]-----------------------------

    This utility has selected a 100- or 510-class product.

    This utility will load the adapter 'jioserdesusb.dll'.

    The library build date was 'Aug 20 2013'.

    The library build time was '22:56:19'.

    The library package version is '5.1.232.0'.

    The library component version is '35.34.40.0'.

    The controller does not use a programmable FPGA.

    The controller has a version number of '4' (0x00000004).

    The controller has an insertion length of '0' (0x00000000).

    This utility will attempt to reset the controller.

    This utility has successfully reset the controller.

    -----[Print the reset-command hardware log-file]-----------------------------

    The scan-path will be reset by toggling the JTAG TRST signal.

    The controller is the FTDI FT2232 with USB interface.

    The link from controller to target is direct (without cable).

    The software is configured for FTDI FT2232 features.

    The controller cannot monitor the value on the EMU[0] pin.

    The controller cannot monitor the value on the EMU[1] pin.

    The controller cannot control the timing on output pins.

    The controller cannot control the timing on input pins.

    The scan-path link-delay has been set to exactly '0' (0x0000).

    -----[The log-file for the JTAG TCLK output generated from the PLL]----------

    There is no hardware for programming the JTAG TCLK frequency.

    -----[Measure the source and frequency of the final JTAG TCLKR input]--------

    There is no hardware for measuring the JTAG TCLK frequency.

    -----[Perform the standard path-length test on the JTAG IR and DR]-----------

    This path-length test uses blocks of 512 32-bit words.

    The test for the JTAG IR instruction path-length failed.

    The JTAG IR instruction scan-path is stuck-at-ones.

    The test for the JTAG DR bypass path-length failed.

    The JTAG DR bypass scan-path is stuck-at-ones.

    -----[Perform the Integrity scan-test on the JTAG IR]------------------------

    This test will use blocks of 512 32-bit words.

    This test will be applied just once.

    Do a test using 0xFFFFFFFF.

    Scan tests: 1, skipped: 0, failed: 0

    Do a test using 0x00000000.

    Test 2 Word 0: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 1: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 2: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 3: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 4: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 5: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 6: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 7: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    The details of the first 8 errors have been provided.

    The utility will now report only the count of failed tests.

    Scan tests: 2, skipped: 0, failed: 1

    Do a test using 0xFE03E0E2.

    Scan tests: 3, skipped: 0, failed: 2

    Do a test using 0x01FC1F1D.

    Scan tests: 4, skipped: 0, failed: 3

    Do a test using 0x5533CCAA.

    Scan tests: 5, skipped: 0, failed: 4

    Do a test using 0xAACC3355.

    Scan tests: 6, skipped: 0, failed: 5

    Some of the values were corrupted - 83.3 percent.

    The JTAG IR Integrity scan-test has failed.

    -----[Perform the Integrity scan-test on the JTAG DR]------------------------

    This test will use blocks of 512 32-bit words.

    This test will be applied just once.

    Do a test using 0xFFFFFFFF.

    Scan tests: 1, skipped: 0, failed: 0

    Do a test using 0x00000000.

    Test 2 Word 0: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 1: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 2: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 3: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 4: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 5: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 6: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    Test 2 Word 7: scanned out 0x00000000 and scanned in 0xFFFFFFFF.

    The details of the first 8 errors have been provided.

    The utility will now report only the count of failed tests.

    Scan tests: 2, skipped: 0, failed: 1

    Do a test using 0xFE03E0E2.

    Scan tests: 3, skipped: 0, failed: 2

    Do a test using 0x01FC1F1D.

    Scan tests: 4, skipped: 0, failed: 3

    Do a test using 0x5533CCAA.

    Scan tests: 5, skipped: 0, failed: 4

    Do a test using 0xAACC3355.

    Scan tests: 6, skipped: 0, failed: 5

    Some of the values were corrupted - 83.3 percent.

    The JTAG DR Integrity scan-test has failed.

    [End]

    2.RTCK上有时钟回来,但和正常能连接仿真器的板卡不一样,正常连接上仿真器后RTCK电压为0,我的板卡显示是1.75V.如下图第一张图是连接不上仿真器的RTCK图第二张是正常连接仿真器的RTCK图

    3。TRST引脚没有接到reset引脚上

  • 上面还是测试时报的信息,前面不是有过了吗。 我问的是连接时报的错误信息。

    TCK的电平正常吗?

    电路上将RTCK外部加下拉,因为内部是下拉。

  • 连接时的错误提示:

    tck电平不正常,没有时钟信号一直是高电平3.3V.

    RTCK下拉后没用,还是1.75V

  • user6258583 说:
    tck电平不正常,没有时钟信号一直是高电平3.3V.

    怎么判断不正常的?没有时钟信号是什么意思?RTCK来源于TCK,没有TCK,又哪来的RTCK呢?

  • 1.我对比了能连接上仿真器的板卡,能连接上仿真器的板卡,测试连接的时候TCK和RTCK的信号一样,从3.3v变成0V然后有两个上升沿信号到3.3V。
    2.我的板卡测试连接时只有RTCK有上面显示的从1.75V到3.3v的上升沿,tck一直是3.3V没有变化
    3.电路中RTCK上没有接下拉电阻,接上4.7K下拉之后没有拉到地,测试连接时还是显示的从1.75V到3.3v的上升沿
  • 我想问一下,RTC不用时芯片手册上说 RTC_XI (May be held high (CVDD) or low)这个是必须要接到地或者CVDD吗?如果不接会有影响吗?我的板卡这个引脚没有接,这会不会是JTAG连接不上的原因?
  • RTC_CVDD不接会影响仿真器的连接,RTC时钟没关系。

  • RTC_CVDD是接着的,所有的电源都接了,现在真的不知道是什么问题了

  • 我想问下除了电源,还有其他输入脚需要注意的会影响仿真器连接的吗?
  • 你5块有2块可以连,所以原理图上应该没什么问题吧.

    板子上焊的芯片是不是同一个版本? 不会是焊了加密版本的芯片吧

  • 是五块都有这个问题,之前只试了三块,所以我怀疑是原理图问题,但现在找不到问题
  • 能不能一次把我问的两个问题一起回答了? 真累

    板子上焊的芯片是不是同一个版本? 不会是焊了加密版本的芯片吧

  • 焊接的芯片是一样的,怎样判断芯片是不是加密版的?
  • 拍个照片上来.
  • 芯片是正常的通用芯片,不是加密版本的。

    你有说过正常能连的板子,是开发板,还是以前做的板子?

    还有你说TCK上没信号,我一直有怀疑,因为TCK是从仿真器送出去的,这个无论如何都是应该有的,除非这个脚跟哪里短路了。

  • 正常能连接的板子是开发板
  • 方便把DSP相关电路图发上来吗?

  • 附件为DSP部分原理图,麻烦您帮忙看一看,非常感谢!!!

  • 看不出明显问题,只是好奇为什么不直接用TI提供的symbol,或者直接在LCDK板子的源文件上修改。 再回过头来查为什么TCK信号一直为高(希望没记错)。

    #1. 用万用表量一下TCK与3.3V之间有没有短路。

    #2. 在JTAG test操作时,分别量一下TRST, TMS, TCK, RTCK的信号,看一下信号电平

    #3. 如果上面测试TCK还是没信号,不连板子,在测试模式时,看仿真器端TCK是否有信号?

    另外OSCIN的输入时钟电平是多高?信号是否正常?

  • 你这个JTAG的连接头座子封装上的引脚有没有反? 看一下PCB上1脚是在哪边? 在PCB上截个图看一下.

  • 1.TCK没有和3.3V短路

    2.

    TCK:一直是高电平

    RTCK:不插仿真器3.3v.插上仿真器1.75v JTAG test 时有两个上升沿信号(接了下拉电阻)

    TRST:不插仿真器0v,插上仿真器变成3.3v,JTAGtest无变化。

    TMS:不插仿真器3.3V.插上仿真器为0V.JTAG test 时有2.8s的上升沿信号。

    3.不连板子仿真器端测试连接时:

    TCK低电平无信号

    RTCK低电平,有两个50ms的上升沿信号。

    4.OSCIN电平2.8V,信号正常。24MHZ

    5.JTAG口PCB引脚顺序正常

  • 好像找到问题了。你的座子上的TCK 与RTCK接反了。下面右图是LCDK的。左图是你的。

    有两种方法可以改:

    #1.飞线改,这个你自己想办法。

    #2. 在DSP芯片端将RTCK的电阻断开。在JTAG座子那里将TCK与RTCK短路接到一起就可以了。同时将前面提到的RTCK上加的下拉电阻去掉就可以了。

  • 啊啊啊啊啊,非常感谢您抽出宝贵的时间帮我解决问题!!!!也向您学习了很多,再次感谢!!!