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最近想要实现SRIO的驱动,参考PDK的例程时看到关于SRIO_Socket的配置,最终的包应该也是用SRIO_Socket发送出去的,请问:
1. SRIO_Socket是一个什么样的概念?在论坛或是百度搜索没有看到相关的解释
2. 从手册看,除了type9 stream和type11 message需要用到QMSS和CPPI,其他type的发送应该是用不到的,通过直接配置LSU就可以实现发送,那么一样通过SRIO_Socket发送,
(1)SRIO_Socket用到了QMSS和CPPI对吗
(2)是因为它对数据的打包比较方便吗
3. 例程有通过CSL和API实现的,SRIO手册是直接对寄存器进行配置的,看了半天有点糊涂,想要实现基础的NWRITE NREAD DOORBELL,如果是从SRIO_Socket这条路走,请问有什么建议吗
还请不吝赐教,谢谢!
谢谢!文档很有启发作用,但是几个问题:
1. 对于SRIO的端口(port)设置是怎么实现的呢?比如只想用一对RXTX是怎么设置呢?
下面是例程中device_srio_loopback.c的代码
/* Enable TLM Base Routing Information for Maintainance Requests & ensure that
* the BRR's can be used by all the ports. */
CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 0, 1, 1, 1, 0);
CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 0, 2, 1, 1, 0);
CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 0, 3, 1, 1, 0);
CSL_SRIO_SetTLMPortBaseRoutingInfo(hSrio, 1, 0, 1, 1, 0);
/* Configure the Base Routing Register to ensure that all packets matching the
* Device Identifier & the Secondary Device Id are admitted. */
CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 0, 1, DEVICE_ID2_16BIT, 0xFFFF);
CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 0, 2, DEVICE_ID3_16BIT, 0xFFFF);
CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 0, 3, DEVICE_ID4_16BIT, 0xFFFF);
CSL_SRIO_SetTLMPortBaseRoutingPatternMatch(hSrio, 1, 0, DEVICE_ID2_8BIT, 0xFF);
以上代码和port的配置是什么关系呢?
2. 手册的KeyStone Architecture Serial Rapid IO (SRIO)对于RapidIO Feature Support in SRIO中的描述中有Defined as Big Endian这一条,是否在DSP在接收的时候,比如自环,或者从fpga等设备接收还需要进行大小端的转换?
1. 主要是用来配置片内的inbound 的route路由的。可以参考一下附件SRIO编程手册。7266.SRIO_Programming_Performance.pdf
2. SRIO数据是big endian的。如果DSP工作在little endian模式的话,SRIO接口会把数据自动转换成big endian。FPGA那边如果是小端模式的话,需要转换成大端。