This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

关于K2G中的DSP C66xx cache使用问题

Other Parts Discussed in Thread: 66AK2G12

我的工程要做实时计算,于是准备使用cache功能,通过路径F:\ti\pdk_k2g_1_0_16\packages\ti\csl  分别加入了 <csl.h>   <csl_cache.h>   这两个头文件,工程属性设置里面,ccs build-->include options-->>add dir tro #include search path--> 添加csl所在的路径,然后代码初始化阶段加入如下两个函数:

    CACHE_enableCaching(CACHE_CE00);
    CACHE_setL2Size(CACHE_256KCACHE);

编译时报错,说是无法找到这两个函数,CCS版本是9.3

那是不是我还有些相关头文件没有加入工程造成的呢?另外,我后面有尝试自己配置cahce控制寄存器,在文档SPRUGW0C中关于Level 2Memory and Cache 章节找到了相关寄存器描述,如下:

4.4.2 L2 Configuration Register (L2CFG)
The L2CFG register controls operating the L2 cache. The L2CFG sets the amount of L2
memory that acts as cache, controls L2 freeze modes, and holds L1D/L1P invalidate
bits.
The L2 configuration register (L2CFG) is shown in Figure 4-3 and described in
Table 4-10.
Table 4-9 Cache Control Registers
Address Acronym Register Description Section
0184 0000h L2CFG L2 Configuration Register Section 4.4.2
0184 4000h L2WBAR L2 Writeback Base Address Register Section 4.4.3.1.1
0184 4004h L2WWC L2 Writeback Word Count Register Section 4.4.3.1.2
0184 4010h L2WIBAR L2 Writeback-Invalidate Base Address Register Section 4.4.3.1.3
0184 4014h L2WIWC L2 Writeback-Invalidate Word Count Register Section 4.4.3.1.4
0184 4018h L2IBAR L2 Invalidate Base Address Register Section 4.4.3.1.5
0184 401Ch L2IWC L2 Invalidate Word Count Register Section 4.4.3.1.6
0184 5000h L2WB L2 Writeback Register Section 4.4.3.2.1
0184 5004h L2WBINV L2 Writeback-Invalidate Register Section 4.4.3.2.2
0184 5008h L2INV L2 Invalidate Register Section 4.4.3.2.3
Figure 4-3 L2 Configuration Register (L2CFG)
31 28 27 24 23 20 19 16
Reserved NUM MM Reserved MMID
R-0 R-config R-0 R-config
15 10 9 8 7 4 3 2 0
Reserved IP ID Reserved L2CC L2MODE
R-0 W-0 W-0 R-0 R/W-0 R/W-0
Legend: R = Read only; W = Write only; -n = value after reset; -x, value is indeterminate — see the device-specific data manual

其中第一个寄存器L2CFG中有个L2MODE控制位

2-0 L2MODE 0-7h Defines the size of L2 cache.
0h L2 cache disabled.
1h 32K
2h 64K
3h 128K
4h 256K
5h 512K
6h 1024K
7h Maximum cache

于是我配置这个控制位,写入参数5,因为工程中我使用了L2_SRAM_0作为运行memory,配置完毕,运行后发现之前的一个算法代码执行时间几乎没任何变化,不知道是不是我对L2CFG配置不正确还是什么缘故,希望TI工程师给予帮助,谢谢