请教关于McASP部分AUXCLK的问题

dadi zeng

大家好：

请问我想从ACLKR1 输出音频左右时钟（48kHz），现在我配置是从AHCLKR分频，而AHCLKR从AUXCLK分频，但我配置完后，发现用示波器观察AHCLKR管脚，无输出，是什么问题？

另外AUXCLK是否需要配置，在哪个寄存器配置？

代码如下：

//Sample data on rising edge since DIR drives data on falling edge
McASP1_ACLKRCTL = (0x1<<7)
| (0x1<<5); //Internal clock source

//---McASP1_AHCLKRCTL default values
McASP1_AHCLKRCTL = (0x1 << 15) //Internal receive high-frequency clock source
| (0x64); //divide ratio is 100

。。。。。

McASP1_PDIR |= (0x1<<31) //AFSR output
| (0x1<<30) //AHCLKR output
| (0x1<<29); //ACLKR output

12 年多前

0 dadi zeng 12 年多前

Intellectual 431 points

加了复位后，ACLKR有了输出，但是AHCLKR还是没有：

while(!(McASP1_GBLCTL & (1<<1)))
{
McASP1_RGBLCTL |= (1<<1); //AHCLK RESET
}

//STEP 6b-c - Take respective serializers out of reset
while(!(McASP1_GBLCTL & (1<<0)))
{
McASP1_RGBLCTL |= (1<<0); //ACLKR RESET
}

0 Shine 12 年多前回复 dadi zeng

TI__Guru**** 357097 points

试试先写RGBLCTL, 再回读GBLCTL寄存器.

McASP1_RGBLCTL |= (1<<1); //AHCLK RESET
while(!(McASP1_GBLCTL & (1<<1)))

McASP1_RGBLCTL |= (1<<0); //ACLKR RESET
while(!(McASP1_GBLCTL & (1<<0)))

McASP文档上有说明.
4. Start the respective serial clocks ACLKX and/or ACLKR. This step can be skipped if external serial
clocks are used and they are running:
a. Take the respective internal serial clock divider(s) out of reset by setting the RCLKRST bit for the
receiver and/or the XCLKRST bit for the transmitter in GBLCTL. All other bits in GBLCTL should be
left at the previous state.
b. Read back from GBLCTL to ensure the bit(s) to which you wrote are successfully latched in
GBLCTL before you proceed.

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请教关于McASP部分AUXCLK的问题