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SRIO接口速率问题



TI STK提供的测试结果,使用4X 5G SRIO链路,SWRITE情况下,SL2发送DDR接收时速率约1500MB/S,但是DDR发到DDR时的速率会降低到1100MB/S左右。

我们使用下来实测也是这个结果,请问这是什么原因造成的?感觉瓶颈不应该在DDR那边,DDR工作在1333MHZ下的。