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存储区域为DDR；
核1写完，cacheWb；核2写完，cacheWb；核0cacheInv，再读取；
为什么两个核心写入的数据不能全读出来呢？
是因为缺少同步和互斥信号量吗？
核0读数程序
for (i = 0;i<5*3;i++){ if(i>2){ cacheInv((inBuf1+i*3+2),32,TRUE); } L1[i] = *(inBuf1+i*3+2); peak_save[i] = L1[i]; if(i>2){ cacheInv((inBuf1+i*3),32,TRUE); } L2222[i] = *(inBuf1+i*3); if(i>2){ cacheInv((inBuf1+i*3+1),32,TRUE); } L33333[i] = *(inBuf1+i*3+1); }
核1和核2写数程序，执行如下的程序 int j=0,p=0,q = 0; for(i = 0;i < 3*3;i++){ if(i%3 == 0){ *(inBuf1 + 3*3*coreId+i)=xxxxxxx[j]; cacheWb(inBuf1 + 3*3*coreId+i,32,1); j = j + 1; } else if(i%3 == 1){ *(inBuf1 + 3*3*coreId+i)=yyyyyyyy[p]; cacheWb(inBuf1 + 3*3*coreId+i,32,1); p = p + 1; } else{ *(inBuf1 + 3*3*coreId+i)=zzzzzzzz[q]; cacheWb(inBuf1 + 3*3*coreId+i,32,1); q = q + 1; } }
core1写入共享内存情况
00000000 00000000 00000000 00000000 0000000000000000 00000000 00000000 00000000 3F8000003F800000 3F800000 3F800000 3F800000 3F8000003F800000 3F800000 3F800000 00000000 0000000000000000 00000000 00000000 00000000 0000000000000000 00000000 00000000 00000000 0000000000000000 00000000 00000000 00000000 00000000
core2写入共享内存情况
00000000 00000000 00000000 00000000 0000000000000000 00000000 00000000 00000000 0000000000000000 00000000 00000000 00000000 0000000000000000 00000000 00000000 3F800000 3F8000003F800000 3F800000 3F800000 3F800000 3F8000003F800000 3F800000 00000000 00000000 0000000000000000 00000000 00000000 00000000 00000000
core0 读取共享内存情况
能帮忙解决一下吗？急！！！
