edma可以在DDR不同地址上传输，但是无法在DDR和L2 SRAM之间传输？

代码如下

static int size = 256;
#pragma DATA_ALIGN(src, CACHE_L2_LINESIZE)
#pragma DATA_ALIGN(dst, CACHE_L2_LINESIZE)
static float src[256];
static float dst[256];

int mem2mem() { // success
	float *p1 = (float*) 0x80000600;
	float *p2 = (float*) 0x80000f00;
	edma_transfer((Uint32)p1, (Uint32)p2, size * 4);
	return 0;
}

int mem2cache() { // failed
	float *p1 = (float*) 0x80000600;
	edma_transfer((Uint32)p1, (Uint32)dst, size * 4);
	return 0;
}

int cache2mem() { // failed
	float *p2 = (float*) 0x80000f00;
	edma_transfer((Uint32)src, (Uint32)p2, size * 4);
	return 0;
}

    /* Setup the parameter entry parameters (Ping buffer) */
    myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
                                             CSL_EDMA3_TCCH_DIS, \
                                             CSL_EDMA3_ITCINT_DIS, \
                                             CSL_EDMA3_TCINT_EN,\
                                             0, CSL_EDMA3_TCC_NORMAL,\
                                             CSL_EDMA3_FIFOWIDTH_NONE, \
                                             CSL_EDMA3_STATIC_EN, \
                                             CSL_EDMA3_SYNC_A, \
                                             CSL_EDMA3_ADDRMODE_INCR, \
                                             CSL_EDMA3_ADDRMODE_CONST );
    myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0,0);
    myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);
    myParamSetup.linkBcntrld= CSL_EDMA3_LINKBCNTRLD_MAKE(0xFFFF,0);
    myParamSetup.cCnt = 1;

/*
 *  Linker command file
 *
 */

-c
-heap  0x4000
-stack 0x4000

/* Memory Map 1 - the default */
MEMORY
{
    L1PSRAM (RWX)  : org = 0x0E00000, len = 0x7FFF
    L1DSRAM (RWX)  : org = 0x0F00000, len = 0x7FFF 

    L2SRAM (RWX)   : org = 0x0840200, len = 0x1FE00
    MSMCSRAM (RWX) : org = 0xc000000, len = 0x200000
    DDR3 (RWX)     : org = 0x80000000,len = 0x10000000
    L2SRAM_CINT00(RWX)  : org = 0x0840000, len = 0x00200
}

	
SECTIONS
{
	.text:_c_int00   >       L2SRAM_CINT00
    .csl_vect   >       L2SRAM
    .version    >       L2SRAM
    platform_lib>       L2SRAM
    .text       >       L2SRAM
    GROUP (NEAR_DP)
    {
    .neardata
    .rodata 
    .bss
    } load > L2SRAM
    .stack      >       L2SRAM
    .cinit      >       L2SRAM
    .cio        >       L2SRAM
    .const      >       L2SRAM
    .data       >       L2SRAM
    .switch     >       L2SRAM
    .sysmem     >       L2SRAM
    .far        >       L2SRAM
    .testMem    >       L2SRAM
    .fardata    >       L2SRAM
}