This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

omapl138 starterware uart2 波特率异常

Other Parts Discussed in Thread: OMAP-L138

工程师您好!

参考starterware的例程,

硬件是参考omap-l138 lcdk设计的。

用仿真器加载后,uart2打印乱码,示波器测量波特率为77K;

代码如下:

void main(void)
{
int i;
// 初始化串口终端 使用串口2
UARTStdioInit();
UARTprintf( "\r\n" );
UARTprintf( "=================================================\r\n" );

不确定是哪里出了问题,请指导一下,谢谢!

  • 请问跑的是哪个例程?串口终端设置的是 115200 baud, no parity, 1 stop bit and no flow control吗?
  • 感谢回复!
    只是将UARTStdioInit();和UARTprintf( "\r\n" );
    拷贝到自己的工程,
    串口终端是上文提到的设置。
    有一个现象是使用SD卡启动linux是可以这打印的。
    会不会硬件上有要求呢?
  • 请问直接跑uart例程能打印吗?
  • Hi Shine,感谢回复!
    我安装了starterware, 但里面只有源码,所以只能网上找了其他例程进行修改。
    如果有官方的例程,麻烦告知下载路径,感谢!
    确实也有点怀疑是不是加载和配置的操作有问题,目前还确认不到。
  • 请看一下#include "uartStdio.h"头文件有没有添加。
  • 应该是.gel文件中将主频设为456了,实际器件只有375,将PLL0的乘数降了一些,就可以正常打印了
    感谢!
  • 感谢分享解决方法!
  • Hi, Shine:

    是否可以分享一个375MHz 所需的.gel配置文件。(可能是PLL0片的错误)

    我的gel文件中关于PLL0的配置如下,375MHz的PLLM最大只能到11,再大串口就乱码了,但配为11应该没有跑到最高主频,是否可以提供一组PLL0配置,可以达到最快频率的?

    谢谢!

    Set_Core_456MHz() {
    device_PLL0(0,18,0,0,1,3,9);
    GEL_TextOut("\tPLL0 init done for Core:456MHz, EMIFA:114MHz\n","Output",1,1,1);
    }

    Set_Core_375MHz() {
    device_PLL0(0,11,0,0,1,3,9);
    GEL_TextOut("\tPLL0 init done for Core:375MHz, EMIFA:114MHz\n","Output",1,1,1);
    }

    device_PLL0(unsigned int CLKMODE, unsigned int PLLM, unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3, unsigned int PLLDIV7 ) {

    unsigned int i=0;

    /* Clear PLL lock bit */
    CFGCHIP0 &= ~(0x00000010);

    /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
    PLL0_PLLCTL &= ~(0x00000020);

    /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
    PLL0_PLLCTL &= ~(0x00000200);

    /* Set PLLEN=0 to put in bypass mode*/
    PLL0_PLLCTL &= ~(0x00000001);

    /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
    for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

    /* Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
    PLL0_PLLCTL &= 0xFFFFFEFF;
    PLL0_PLLCTL |= (CLKMODE << 8);

    /*Clear PLLRST bit to reset the PLL */
    PLL0_PLLCTL &= ~(0x00000008);

    /* Disable the PLL output*/
    PLL0_PLLCTL |= (0x00000010);

    /* PLL initialization sequence
    Power up the PLL by setting PWRDN bit set to 0 */
    PLL0_PLLCTL &= ~(0x00000002);

    /* Enable the PLL output*/
    PLL0_PLLCTL &= ~(0x00000010);

    /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
    for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

    /*Program the required multiplier value in PLLM*/
    PLL0_PLLM = PLLM;

    /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
    PLL0_POSTDIV = 0x8000 | POSTDIV;

    /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
    while(PLL0_PLLSTAT & 0x1==1){}

    /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
    PLL0_PLLDIV1 = 0x8000 | PLLDIV1; // Fixed Ratio /1
    PLL0_PLLDIV2 = 0x8000 | PLLDIV2; // Fixed Ratio /2
    PLL0_PLLDIV4 = 0x8000 | (((PLLDIV1+1)*4)-1); // Fixed Ratio /4
    PLL0_PLLDIV6 = 0x8000 | PLLDIV1; // Fixed Ratio /1
    PLL0_PLLDIV3 = 0x8000 | PLLDIV3; // Variable Ratio (EMIF)
    PLL0_PLLDIV7 = 0x8000 | PLLDIV7; // Variable Ratio (RMII)


    /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
    PLL0_PLLCMD |= 0x1;

    /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
    while(PLL0_PLLSTAT & 0x1==1) { }

    /*Wait for PLL to reset properly.*/
    for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}

    /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
    PLL0_PLLCTL |= 0x8;

    /*Wait for PLL to lock.*/
    for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;}

    /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
    PLL0_PLLCTL |= 0x1;
    }

  • 可以参考C:\ti\ccs1020\ccs\ccs_base\emulation\boards\evmomapl138\gel里的配置,用的是24MHz,最高配到300MHz,但PLLM是大于11的。
  • Hi Shine:

    还是有些异常:

    使用如下代码,使用仿真器,直接在arm上运行,如果gel文件中PLL0配置主频为456MHz串口打印正常,如果修为其他主频(器件是365MHz),则是波特率异常;不知道是哪里影响了串口波特率啊?

    int main(void)
    {
    int i,j,target_int_count=2;
    char ch[2];
    
    /* 初始化串口终端 使用串口2*/
    UARTStdioInit();
    
    /* 打印串口终端信息*/
    UARTPuts("Test Application.\r\n", -2);

    感谢!

  • 如果您用的器件实际只有375MHz, gel文件中不要把主频设为456,不建议超频使用。
x 出现错误。请重试或与管理员联系。